利用類比電路自動佈局設計實現低壓差穩壓器

Abstract

現今IC(Integrated Circuit)的製程技術演進，顧客需求使晶片在設計週期減少。包含數位及類比電路的設計越來越多元件，製程參數及佈局考量都影響成敗。因為寄生效應對於電路效能的影響並未考慮進去，導致耗費了相當多的時間重複調整設計。而在類比數位混合訊號的設計中，因為外在環境訊號都是類比的關係，所以類比部分是無法避免的。目前數位電路的自動化軟體工具已經發展得相當成熟，然而類比訊號自動化設計工具並不是相當常見。主要是因為類比電路有較多限制，較難實現最佳化的工具，類比電路設計往往成為整個類比電路設計快速發展的瓶頸。 佈局的擺置對於類比及混合訊號IC電路效能有很大的影響，因此擺置的結果非常重要。為了得到高效能的電路佈局，必須考慮許多佈局擺放關係的特殊限制，這也是為什麼類比電路佈局還無法完全自動化的原因。至今類比電路佈局大都還是由工程師手動佈局為主，需要花相當多時間才能完成整個設計。因此要加速整個IC設計過程，輔助設計工具是不可或缺的。本論文是以設計類比電源管理IC為實驗電路，提出一個實現類比自動佈局的方法。此方法可以幫助自動放置或是繞線可以參考現有佈局（Template-Based Layout）得到新製程的佈局。將新產生佈局與手動繪製佈局圖比較，藉由 Calibre XRC 工具執行Post-simulation的模擬比較各製程的佈局差異。類比佈局結果也要能達到預期的電源管理IC效能，可應製程改變達到快速產生佈局。 根據電源管理IC所做的實驗結果顯示，我們所提出的階層式類比元件擺置方法和過去文獻中所提的方法相比較，在保留原來佈局特性和接近等類比元件擺置限制條件最有效率，同時可以在最短的時間內，得到最佳的類比電路效能及精確性。

Because of modern IC’s (Integrated Circuit) development, clients request less chip usage during the design cycle. Since designs that include digital and analog circuits have more and more components, process parameters and layout considerations affect its success or failure. Because the performances of the parasitic circuits are not taken into account, it leads to a considerable amount of time loss to readjust the design. In analog-digital mixed-signal design, because the external environment’s signals are all analog, so the analog signal portion is unavoidable. Currently, digital circuit automation software has developed quite well, however, analog circuit automation software is quite uncommon, due to having more restrictions, therefore, it is harder to achieve its maximum potential. Because of this, analog’s circuit design often becomes the bottleneck of the rapid development of analog signal’s advancement. The layout placement has a great impact to analog and mixed-signal IC circuits, therefore the placement is very important. To achieve efficient analog’s layout, we must consider many precise restrictions in placing the layout. This is also one of the reasons why analog circuit layouts cannot be fully automated. So far, most of the analog circuit’s layout is manually designed by engineers, which takes a considerable amount of time to complete the whole chip. Therefore, to accelerate the whole chip design process, we must not dispense design-assisted tools. This abstract is based on the experimental circuit of the design of analog power management IC, to provide a method to achieving analog’s automated layout. This method can help automatic placement or routing, which can refer to the template-based layout to achieve the layout of the new process. In comparison of the new layout with the hand-drawn layout, we use Mentor- Calibre-XRC tool to run the post-simulation to differentiate each layout. The analog layout also has to achieve the expected performance of the power management IC, which may be due to the process changing to quickly produce layouts. According to the experiment results from the power management IC, we propose a hierarchical placement method of the analog component placement and compared it with the past document’s method. While retaining the original layout characteristics and proximity, analog component layout restriction is the most efficient, while in the shortest time possible achieving the best analog layout performance and accuracy.