針對多執行緒/多核心模擬器之動態調整機制與部分取樣策略

Abstract

模擬器被廣泛使用於硬體架構上的探索以及軟體應用程式的驗證，然而，在正確率以及效能之間的取捨限制住模擬器的發展，在單一核心上，傳統取樣能夠有效減少模擬器的模擬時間並保持一定的準確率，但是在多執行緒或是多核心架構上卻不適用，因此，此篇論文建立一個可以動態調整機制加上部分取樣策略來彌補傳統取樣在多執行緒或多核心架構的不足。首先，考慮到在多執行緒下各個執行緒的干擾，本篇論文增加一個積極取樣機制以捕捉程式行為變化較大的部分；另外，為了減少不必要的效能負擔，藉由區域性位相偵測來驅動鬆散的取樣機制；最後，本篇論文提出部分取樣策略來維持快取記憶體一致性的正確率。

Simulations are widely used for exploring hardware architectures or validating software applications. The trade-off between performance and accuracy let simulations are limited. Sampling can effectively reduce simulation time and still keep high accuracy for single core. However, conventional sampling does not suitable for multi-threaded application or multi-core architecture. Therefore, this thesis builds a dynamic adjustment and partial sampling (DAPs) to make up the shortcoming of conventional sampling. In order to overcome thread interferences in multi-thread application, DAPs adds an aggressive sampling for capturing the high variability of program behavior. Furthermore, DAPs proposes a lazy sampling to find the locality-phase behavior and reduce the unnecessary overhead. Finally, DAPs partially selects sampling core for keeping the accuracy of cache coherence.