標題: 堆疊型閘極介電質及銦鎵鋅氧化物雙通道結構應用於薄膜電晶體之研究
Investigation of Metal-Oxide InGaZnO Thin Film Transistors Using Stacked Gate Dielectrics and Dual Channels
作者: 徐曉萱
Hsu, Hsiao-Hsuan
張俊彥
Chang, Chun-Yen
電子工程學系 電子研究所
關鍵字: 銦鎵鋅氧化物;軟性薄膜電晶體;雙通道層;InGaZnO;Flexible Thin Film Transistor;Dual-Channel layer
公開日期: 2013
摘要: 銦鎵鋅氧化物(InGaZnO, IGZO)薄膜電晶體具有高載子遷移率、低成本、低製程溫度以及高均勻度等優點,可整合軟性顯示器或積體電路等應用,其特性能與非晶矽和多晶矽薄膜電晶體相抗衡,因此近幾年來已引起全球產學研各方的關注。然而,傳統的IGZO薄膜電晶體具有高操作電壓、高次臨界擺幅以及低載子遷移率(< 20 m2/Vs)特性,會限制高速以及高解析度的顯示器發展。因此,本論文提出兩種閘極堆疊工程策略來改善薄膜電晶體元件特性,研究內容包含堆疊式閘極介電層結構,以及新型雙層通道結構。 在閘極介電層堆疊結構設計上,本研究成功整合具有非常高介電常數的二氧化鈦(TiO2)薄膜於IGZO薄膜電晶體。藉由高介質二氧化鈦來增強閘極控制力,以改善元件操作電壓,以及驅動電流。本論文所提出的堆疊型閘極介電質結構為三層式介電質,薄膜結構分別為三氧化二釔/二氧化鈦/三氧化二釔(Y2O3/TiO2/Y2O3)和二氧化矽/二氧化鈦/二氧化矽(SiO2/TiO2/SiO2)。此三層式閘極介電質結構可在近室溫下沉積,適用於軟性基板製程。實驗結果指出,整合三層式閘極介電質之IGZO薄膜電晶體,具有較陡峭的次臨界擺幅 (129~137 mV/decade)、較低的臨界電壓 (0.5~0.75 V)、較高的載子遷移率 (32~76 cm2/Vs) 以及較低的操作電壓 (2~3 V)。此外,此三層式可撓式薄膜電晶體元件經由15毫米的彎曲測試後,仍保持良好的電晶體元件特性,足以證明室溫下製作之二氧化鈦基(TiO2-based)堆疊型閘極介電層,可成功應用於低溫且可撓性之IGZO薄膜電晶體製作。其優異的元件特性主要是源自於高介電常數的二氧化鈦薄膜增加閘極控制能力,以及銦鎵鋅氧化物通道層的厚度調變改善了元件關閉電流。 我們也同步透過雙通道結構的設計來改良元件特性,本文提出一種具鈦摻雜的銦鎵鋅氧化物半導體(IGZO:Ti)來做為通道覆蓋層,與傳統IGZO通道相結合,形成新型雙層通道結構(IGZO/IGZO:Ti)。利用上層的IGZO:Ti覆蓋層做為氧原子的吸附層,透過IGZO:Ti和IGZO厚度調變,可大幅改善載子遷移率以及電晶體開關特性。此新通道薄膜電晶體特性,可達到小的次臨界擺幅 (73 mV/decade)、高的載子遷移率 (63 cm2/Vs) 以及低的操作電壓 (2 V)。另一種新型雙通道結構,則是直接利用氧化鈦(TiOx)作為IGZO通道之覆蓋層。經最佳化後的5奈米高介電常數TiOx 覆蓋層可提供最佳的閘極控制能力,可在較低的閘極偏壓下,達到最大化載子累積程度和較高的載子遷移率。此外,經由強化橫跨於IGZO通道之垂直電場,在負偏操作時,也可獲得較佳的載子空乏效應,來改善電晶體關閉特性。因此,藉由一個適當TiOx覆蓋層厚度調變,可有效改善閘極控制能力,得到較好的IGZO電晶體元件特性,此元件可達到較小的次臨界擺幅 (77 mV/decade)、較高的載子遷移率 (55 cm2/Vs)、較小的臨界電壓 (0.37 V) 以及較低的操作電壓 (2 V)。 根據閘極介電層和通道調變工程的實驗結果,利用堆疊的閘極介電層或是新型雙通道結構,整合低成本TiOx薄膜至銦鎵鋅氧化物電晶體,將具有應用於下世代高解析度及低功率顯示器的潛力。
InGaZnO-based thin film transistors have attracted increasing attention in recent years because of the relatively low cost and good uniformity compared to the amorphous-silicon and poly-silicon TFTs. Besides, IGZO TFTs can be processed with a low thermal budget that has the capability of integrating flexible displays and low-cost flexible ICs. However, IGZO TFTs on flexible substrates showed large operating voltage, high sub-threshold swing, and low mobility, which limit the applications for high-resolution and high-speed displays. Therefore, in this dissertation, we bring up the methodology of gate dielectric and channel engineering, devoting into two main categories, namely the stacked gate dielectrics and dual-channel layers, to improve the electrical performance. In the aspect of stacked gate dielectrics, we proposed the flexible amorphous IGZO TFTs with very high- TiO2 incorporation fabricated at room temperature. The IGZO TFT with tri-layer gate dielectrics of Y2O3/TiO2/Y2O3 and SiO2/TiO2/SiO2 show a small sub-threshold swing of 129~137 mV/decade, a low threshold voltage of 0.5~0.75 V, a high field effect mobility of 32~76 cm2/Vs and a good on/off current ratio of 6.7´105~1.7´106 under an operating voltage of 2~3 V on the flexible polycarbonate substrates. To further evaluate bending flexibility, the bending test with the radius from 35 mm to 15 mm was performed, showing only slightly degraded sub-threshold swing and device mobility. The results demonstrated the feasibility of room-temperature IGZO TFT using tri-layer gate dielectric because of the combined effect of improved TiO2-based dielectric stack and IGZO thickness modulation, which allow for flexible device fabrication even at room temperature. In the aspect of dual-channel structure design, the high mobility metal-oxide TFT using bilayer channel structure of IGZO/Titanium-Doped InGaZnO (IGZO/IGZO:Ti) was proposed. The top IGZO:Ti capping layer that incorporates Ti can be used as an oxygen gettering layer to enhance device mobility and also greatly improve transistor switching characteristics. The good transistor performance of the lowest drive voltage (VG-VT) of < 2V, smallest sub-threshold swing of 73 mV/decade, and highest field effect mobility of 63 cm2/Vs can be achieved in this novel TFTs with the thickness modulation of IGZO:Ti. Another dual channel scheme of IGZO TFT with TiOx capping layer was also demonstrated. The higher- TiOx capping provides better gate control capability to maximize charge accumulation and reach higher electron mobility under lower gate biasing. Furthermore, the optimized 5-nm-thick TiOx can enhance vertical field across IGZO channel to improve the turn-off characteristics due to better carrier depletion effect at a negative bias. Thus, an appropriate modulation on TiOx thickness leads to favorable gate control ability, which provides improved transistor characteristics of a low drive voltage of < 2 V, a low threshold voltage of 0.37 V, a low sub-threshold swing of 77 mV/decade, and a high mobility of 55 cm2/Vs. According to our experimental results, the integration of low-cost TiOx film into the gate dielectric and channel layer of IGZO TFT are suitable for the applications of next-generation displays with high resolution and low power consumption.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079811802
http://hdl.handle.net/11536/74231
顯示於類別:畢業論文