具懸浮奈米線通道之場效電晶體和多晶矽奈米線互補式金氧半反相器的研製與特性分析

Abstract

在本篇論文中，我們成功地研製兩種新穎的元件結構，分別為具懸浮式奈米線通道之場效電晶體 (suspended-NW-channel FETs)和具側閘極之多晶矽奈米線通道互補式金氧半反相器 (poly-Si NW-channel CMOS inverters)。所提出的奈米線元件是利用本實驗室所發展出一簡易且低成本的側壁邊襯蝕刻法(side-wall spacer etching) 來製作。 對懸浮式奈米線通道之場效電晶體而言，由於有較小的蝕刻深寬比(aspect ratio)結構，因此我們可利用簡易的濕式蝕刻來釋放奈米線通道且形成小於100奈米的空氣間隙(air gap)。我們的結果顯示當通道長度夠短或是空氣間隙夠大時由於釋放製程所造成的stiction現象，可有效地消除。因空氣間隙的存在，我們可使奈米線通道受靜電力吸引而擺動。因此，此類元件可以呈現小於60 mV/dec的次臨界擺幅(subthreshold swing)及遲滯窗口(hysteresis window)之特性。同時我們也發現元件具有震盪的及非對稱的次臨界擺幅。藉由將空氣間隙縮小至10奈米，我們可以將擺入電壓(pull-in voltage)降低至0.65 V。除此之外，藉由分析元件之遲滯特性，我們還發現隨著幾何結構尺寸的改變，如空氣間隙厚度、通道長度、奈米線大小等，各種元件特性都有其特定的變化趨勢。此外，我們提出一個觀念性的模型，以描述元件操作時靜電力(electrostatic force)、彈性回復力(elastic recovery force)與表面黏滯力(surface adhesion force)之間的交互作用來解釋此一現象。 另一方面，藉由討論系統的彈性能(elastic energy)以及表面黏滯能(adhesion energy)之間的關係我們可以推導出一個理論模型來預測及描述實驗上所觀察到的stiction現象。此外，本研究也發展了一個理論模型，可用於描述懸浮式奈米線通道元件之擺入及擺出電壓。藉由此模型，我們可以有效計算並預測出在不同幾何結構尺寸下所對應的擺入電壓與擺出電壓。此外，藉由製程上的些許修改，本研究也成功製作了一種含有矽奈米晶體(Si nanocrystals)嵌入於閘極介電層的新結構，利用此結構有效的使接觸面變得粗糙進而減少表面黏滯力的影響，此一方法可成功地降低擺入電壓以及擺出之次臨界擺幅。更重要的是，利用此結構可以大大地提昇元件的可靠度。 在新開發展的奈米線互補式金氧半反相器中，我們巧妙地利用斜角度離子植佈方式，僅需一道光罩即可完成源極與汲極(source and drain)離子植佈步驟。製作出的n通道及p通道電晶體皆具有高的開關電流比、可接受的次臨界擺幅、及對稱的飽和電流，使得所開發的反相器擁有極佳的電壓轉換特性(voltage transfer characteristics)。藉由控制過蝕刻(over-etching)的時間，我們製備了具有不同尺寸的奈米線元件，用以探討奈米線尺寸對元件電性的影響。我們發現隨著奈米線尺寸的微縮，不僅提升了單一的奈米線電晶體的元件表現同時也改善了反相器的在電路操作時的轉換特性。 然而，藉由觀測元件的輸出特性(output characteristics)，我們發現在n型及p型電晶體上都出現了低飽和電流的問題。其主要原因是由於較窄的奈米線源極與汲極延伸區提高了源極與汲極的串聯電阻。為了提升元件的輸出特性，我們引入鎳矽化物(Ni silicidation)製程來改善高串聯電阻的現象。實驗數據顯示n型及p型元件在飽和電流中分別提升了310%和280%。其主要原因為加入了鎳矽化物製程大大降低了源極與汲極的串聯電阻。

In this dissertation, we have successfully fabricated and investigated two kinds of novel devices, including suspended-nanowire (NW)-channel filed-effect transistors (FETs) and polycrystalline silicon (poly-Si) NW-channel complementary metal-oxide-semiconductor (CMOS) inverters. The proposed NW devices were fabricated by utilizing a simple and low-cost spacer etching technique previously developed by our group. For suspended-NW-channel devices, owing to the small aspect ratio of the etched structure, a simple wet etching process was adopted to release the NW channels and form a sub-100 nm air gap. Our results show that the release-related stiction issue can be eliminated as the channel length is sufficiently short or the air gap is sufficiently thick. The presence of air gap leads to a movable channel operated with electro-mechanical motion. Accordingly, devices with ultra-low subthreshold swing (SS<60mV/dec) and large hysteresis window are demonstrated. The oscillating and asymmetric SS behaviors are also observed. With the aid of a small gap thickness of 10 nm, an ultra-low pull-in voltage of 0.65 V is achieved. Besides, the specific trends of electrical characteristics with different geometric structure dimensions, including gap thickness, channel length, and NW thickness are investigated through hysteresis characteristics. In addition, a conceptual model illustrating the interaction between the electrostatic force, the elastic recovery force and the surface adhesion forces during device operation is also proposed. On the other hand, by considering the relation between the elastic and adhesion energies in the system, an analytical model has been developed to predict and physically describe the stiction phenomenon observed from experimental results. In addition, we also develop an analytical model of pull-in and pull-out voltages (Vpi and Vpo) for suspended-NW-channel FETs by solving force balance equations. Based on the model, the impacts of structural parameters on the Vpi and Vpo can be calculated and predicted. Moreover, a modified approach with incorporated Si nanocrystals (Si NCs) in the gate nitride was also demonstrated in this study. The embedded Si NCs increase the surface roughness, thus reducing the adhesive force as the nitride is in contact with the poly-Si NW channel during the operation. Such a feature results in a reduction in pull-in voltage and sharper pull-out behavior. More importantly, this approach also greatly improves the endurance characteristics of the devices. On the development of new NW CMOS inverters, a clever tilted-angle implantation process in the fabrication was adopted; therefore, the formation of the source and drain (S/D) of both p-channel and n-channel devices requires only one lithographic step. The fabricated n-channel and p-channel FETs in the inverters show a high ON/OFF current ratio, an acceptable SS, and a symmetric driving current, thus enabling the realization of excellent voltage transfer characteristics (VTC) of the inverters. To investigate the effects of the size of NW on device performance, NWs with various widths were fabricated by controlling the duration of over-etching. It is found that significant performance enhancement is feasible on not only discrete NW transistors but also inverter circuits as the dimension of NW channels is reduced. Nevertheless, from the examination of the output characteristics, it is found that both n- and p-FETs exhibits low saturation current. The root cause is identified to be related to the high series S/D resistance (RSD) owing to the narrow width of NW S/D extension regions. In order to obtain high performance in the proposed NW devices, Ni silicidation process was implemented to improve the high RSD issue. Experimental results show that saturation current improvement over control devices are 310% and 280% for n- and p-FETs, respectively. The improvement in output characteristics is attributed to the significant reduction in RSD by applying Ni silicidation process.