無接面奈米線場效電晶體之研究

Abstract

如何製作高良率的奈米線和淺薄又陡峭的半導體接面為未來元件持續微縮所會面臨的重點問題，為了解決短通道和漏電等問題，奈米線被視為未來解決問題的發展方向之一，並且隨著離子佈植的濃度必須提高，半導體接面的濃度梯度如何維持也是元件微縮所會遇到的困境之一，因此無接面電晶體在二零一零年被提出改善這問題。 在此篇論文中首先我們先應用spacer方式製作出我們的無接面奈米線電晶體，並且用熱磷酸進一步的削薄奈米線，最後沉積閘極氧化層與多晶矽完成元件，在此種方法製做出來的電晶體中擁有良好的次臨界擺福、漏電流控制與開關電流比值，但是其奈米線形狀難以控制、閘極引致汲極漏電流嚴重並且其元件特性變動差異廣泛，因此在第二種製程中我們改良製程方法，我們使用TEOS spacer mask去保護底層的奈米線，完成奈米線的製作後去除其多於的氧化層，最後一樣沉積閘極氧化層與多晶矽完成元件製作，由於一開始多了一層遮蔽物保護的關係，此種製程方式製程的元件一樣擁有良好的次臨界擺福、漏電流控制與開關電流比值，另外其大幅改善奈米線形狀的控制問題、減少閘極引致汲極漏電流和減少特性的變動差異，由於上述提到的這些優勢，對於未來元件必須持續微縮的挑戰下，無接面奈米線電晶體是一個很有淺力的發展方向。

Junctionless FETs are of great interest due to the elimination of ultra-shallow junction formation and the reduction of surface roughness scattering. The elimination of ultra-shallow formation is due to the removal of S/D implantation, and the reduction of surface roughness scattering is due to bulk conduction instead of surface conduction. However, nanowire devices suffer from large parasitic resistance as device dimension scaling down. Therefore, we proposed junctionless n+-doping nanowire field-effect transistor (FET) constructed on a gate-all-around structure. Also, These FETs were demonstrated with the raised source/drain to reduce the resistance. We fabricated FETs with novel nanowire channel without the use of advanced lithography tools. First we made the nanowire channel by a TEOS-oxide invert-T dummy layer and a poly-Si spacer. After dry etching, the spacer wire was successfully patterned. Hot phosphorous acid solution was used to remove the dummy TEOS. For FETs, a 7nm TEOS gate oxide was deposited as the gate oxide. The following was in-situ doped n+ poly-silicon deposition as a gate electrode. In the second part, a junctionless FET was fabricated successfully. we fabricated TEOS spacer on the invert-T silicon layer. It was served as the hard mask to protect the Si nanowire. After using hydrofluoric acid to remove the oxide, the gate stacks with 4nm TEOS gate oxide and 200nm poly-Si were deposited. We found that the novel gate-all-around poly-Si junctionless nanowire FETs should show excellent electric characteristics (e.g. high on current, low off-leakage currents, good S.S., improved DIBL, and high on/off ratio).