具奈米結構之新穎氧化物半導體電晶體研究

Abstract

比起傳統的非晶矽半導體，非晶氧化金屬半導體因具有較高載子移動率(~10 cm2/Vs)、較低的工作電壓(<5V)與較小的次臨界擺幅，近年來被視為深具潛力的半導體材料，然而非晶氧化銦鎵鋅薄膜電晶體如果想發展低功率損耗、高頻率操作的電路，則增加其載子移動率，並降低其寄生電容是必要的。在過去的研究中曾提出一個有效的製程方法-奈米點摻雜(Nano-dot doping)搭配雙閘極量測以獲得高載子遷移率之a-IGZO TFTs，本研究中，我們成功地利用奈米壓印製程改善並簡化製程，同時也延長電性提升之效果持續達數周。首先，本論文呈現奈米壓印結構之結果，接著針對參雜度濃度對底閘極電特性之影響進行研究，利用原子層沉積系統成長氧化鋁薄膜，此氧化鋁不僅是上閘極之介電層同時也扮演保護層的角色，雙閘極結構之元件特性接著被引入並進一步釐清a-IGZO TFT特性提升之原因，藉由奈米點狀參雜與雙閘極量測方法，我們得到了不錯的元件特性包括；輸出電流達84.5μA，次臨界擺幅約0.16 V/dec.與106的電流開關比。最後我們持續21天追蹤元件的特性，發現特性提升的效果始終存在。 另一方面，由於垂直式電晶體低成本與高整合性，我們也提出一新穎的垂直式電晶體概念，首先我們製作孔洞化結構之二極體，目的是要驗證二極體通道是否能發展成為電晶體通道，藉由調變電極材料和塗佈製程，我們成功得到具有超高輸出電流密度達577.75 mA/cm2的二極體。接著我們利用模擬軟體建構電晶體模型來確定本概念之可行性，藉由分析通道內電位分佈，我們認為此電晶體概念是可行的，最後電晶體將透過許多製程來完成並量測。

With a higher mobility (>10 cm2/Vs), lower threshold voltage (< 5V) and smaller sub-threshold swing than conventional amorphous silicon semiconductor, amorphous In-Ga-Zn-O thin film transistors (a-IGZO TFTs) has drawn a lot of attention. However, when a-IGZO TFTs are developed for low-power consumption, high-frequency operating of circuit, improved electron mobility and a low parasitic capacitance are required. Previous studies have reported an efficient manufacturing method to obtain a high carrier mobility of a-IGZO TFTs, called “nano-dot doping (NDD)”, with dual-gate measurement. In this thesis, we successfully not only improved and simplified the process by “nano imprint” method but also extended the enhancement effected for several weeks. The imprint-patterned results was firstly demonstrated. The influences of doping concentrations on bottom gate device performance are also investigated. The atomic layer deposition (ALD) system was introduced to create Al2O3, which can not only served as top gate insulator also play an important role as passivation. We then applied dual gate (combine bottom gate with top gate) structure to analyzed the characteristics and clarify the a-IGZO TFTs performance improvement. With NDD and dual gate measurement, the optimized electric characteristic of a-IGZO TFT was attained with output current 84.5μA, sub-threshold swing ~0.16 V/dec., and on/off ratio ~106. Furthermore, the timing constraints of NDD effects was also investigated. After 21 days tracking, the enhancement effects still existed. In addition, a novel vertical transistor concepts is proposed as well, due to its low-cost and easy integration with other devices. First of all, we fabricated a porous structure diodes to demonstrate the channel layer would be available. By altering the electrode materials and coating process, we obtain an ultra-high output current density with 577.75 mA/cm2. A simulation was carried out to prove our concepts can be apply to realistic device. As potential distribution shown in the results, we believed that the concepts are available. At last, the transistor was fabricated in several methods and measured.