一個時脈為1 GHz訊號頻寬50 MHz之十一位元連續時間積分三角調變器

Abstract

超取樣積分三角類比數位轉換器由於具有高動態範圍極低功耗的優點，被廣泛應用在積體電路上。連續時間積分三角調變器因為使用非取樣式的迴路濾波器，所以可以實現高解析度及幾千萬赫茲的頻寬，進而成為在功耗和面積都更有效率的類比數位轉換器。 本論文使用台積電九零奈米製程實現了一個高效率，訊號頻寬五千萬赫茲的連續時間積分三角調變器。此設計使用五階的架構，裡面包含一個主動式電阻電容積分器，兩個單一運算放大器的振盪器以及一個操作在十億赫茲的量化器。為了降低時脈抖動的敏感度，使用了不歸零式的數位類比轉換器。回授路徑的時間延遲被設定為半個取樣頻率週期並使用數位類比轉換器直接回授到量化器輸入作補償。 本論文所提出的連續時間積分三角類比數位轉換調變器在訊號頻寬五千萬赫茲的操作之下可以達到68 dB以上之訊號雜訊比，等效位元解析度為11位元，功率消耗在1V之供應電壓之下為88.9毫瓦且佈局後模擬可知每次轉換的能量為434.1毫微微焦耳。

Oversampling sigma delta (ΣΔ) ADCs are widely used in application-specific ICs due to their high dynamic range and low power consumption. It is feasible to build high resolution continuous time sigma delta ADCs with bandwidth up to tens of MHz due to non-sampling loop filter, leading to more power and area efficient ADCs. In this thesis, a power-efficient continuous time sigma delta modulator (CTSDM) with 50 MHz signal bandwidth implement in TSMC 90 nm CMOS process. To realize such application scenario, the proposed CTSDM comprises a fifth-order loop filter with an active-RC integrator and two single op-amp resonator, and a 4-bit internal quantizer operating at 1 GHz clock frequency. To reduce clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and compensation is achieved by the DAC directly feedback to quantizer input. The proposed CTSDM achieves SNDR equal 68 dB (ENOB 11-bits) over a 50 MHz signal bandwidth. The power consumption is 89.9 mW from a 1 V supply and the energy per conversion is 434.1 fJ from post-layout simulation.