標題: | 利用接觸式塗佈法形成奈米金屬網包覆結構與垂直式空間電荷限制電晶體 Metallic Grid-structure Coverage by Contact Coating and Vertical Space Charge Limited Transistor |
作者: | 鄭羽彣 Cheng, Yu-Wen 孟心飛 Meng, Hsin-Fei 物理研究所 |
關鍵字: | 溶液塗佈;基極包覆;垂直式空間電荷限制電晶體;Coating Process;base coverage;vertical space-charge-limited-transistor |
公開日期: | 2013 |
摘要: | 以濕式塗佈製程塗佈薄膜為一高效率、低成本之技術,近年來被廣泛運用於有機半導體元件製程。目前薄膜塗佈的技術中最廣為人知的技術為旋轉塗佈法(Spin coating)和浸沾式塗佈(Dip coating)。旋轉塗佈法侷限於塗佈平整表面,當塗佈於不規則表面時,會有溶液掉入結構底部或薄膜浮在結構上方的情況發生;而浸沾式塗佈法雖可在不規則表面形成階梯覆蓋(comformal)的結構,但其均勻度不佳且成膜厚度有限,而本實驗室所研發出的接觸式塗佈可藉由液體濃度和抬升速度的控制形成不同的包覆結構,以本實驗室所製備的具奈米金屬網格孔洞結構為例,除了可形成膜厚較厚的階梯覆蓋結構外,還可藉由提高液體濃稠度及降低抬升速度得到柱狀結構上方包覆且保留通道之結構。另外,也可藉由調變基板抬升速度增加附著在基板表面的液體量達到填洞之效果。目前該技術也已應用於本實驗室所開發之垂直式空間電荷限制電晶體( Space Charge Limited Transistor,SCLT),利用基極包覆的方式,增加鋁金屬基極與半導體層之間的位障,降低電晶體在開、關狀態下的漏電流,同時也提升了電晶體的耐壓度,Vc偏壓可從8V提升至15V。接下來本實驗室也會積極改良塗佈機台,希望能提升塗佈穩定度和良率,以便未來能應用在氣體感測元件、IGZO電晶體等其他領域。 Wet-coating process is a high efficiency and low cost technique. It has been widely employed in organic semiconductor device fabrication. The most popular processes are spin coating and dip coating. However, spin coating is limited by the roughness on the substrate surface. When the surface is irregular (column structure), the materials might fill the holes or suspend on the top. Although dip coating can cover the structure surface , It turns out that dip coating does not give a consistent coating morphology and film thickness is still limited. In our laboratory, we developed “contact coating” which can bring out different common coverage structures by controlling the solution concentration and lifting speed. Contact coating can provides a thicker common coverage film structure. Furthermore, by enhancing the solution concentration or lowering the lifting speed, we can obtain the coverage on the top on the column structure and keep the channel between columns as well. On the other hand, in order to fill up the holes between columns, we can modulate the lifting speed to increasing the attached solution on the substrate. Currently, this technique has been used to develop vertical space charge limited transistor, we used this method to cover a insulating thin film on metallic nano-grid surface, such that the leakage current would be less and the collector voltage endurance is greatly enhanced from about 8 V to 15 V. We will improve our equipment to enhance stability and yield, which could be applied on gas sensor or a-IGZO TFTs in the future. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT070152713 http://hdl.handle.net/11536/74994 |
顯示於類別: | 畢業論文 |