氮化矽側壁硬式光罩方法製造多晶矽奈米線非揮發性記憶體元件之特性研究

Abstract

在本篇論文中，為了進一步微縮通道尺寸以及改善其形狀，我們改良了近日所開發的一種製造方法，利用氮化矽側壁硬式光罩(nitride-spacer hardmask)法來形成多晶矽奈米線。兩種方式分別被提出來解決殘留物清除及氮化矽側壁崩解的問題。本研究只採用I-line微影技術就製造出通道長82奈米與邊寬15奈米的奈米線矽-氧化矽-氮化矽-氧化矽-矽(SONOS)元件。由於具有較細的奈米線及閘極全圍繞結構，提供極高的閘極控制能力，元件特性也較先前成果為優，其次臨界擺幅可達72到80 mV/dec，讀/寫效率也相當不錯。此外，以此元件進行雜訊分析，多層級隨機電訊噪音(multilevel random telegraph noise)可被清晰量測與分析。

In this thesis, to further downscale the channel dimensions and improve the device performance, two nitride-spacer hardmask methods ameliorated from a previous fabrication method recently reported by our group have been developed to fabricate nanowire (NW) Si-SiO2-SiN-SiO2-Si (SONOS) devices. Although only I-line lithography was adopted, with the newly developed methods we can fabricate NWs SONOS devices with channel length down to 82 nm and edge width of 15 nm. As a result, the NW devices with GAA structure show better gate controllability as compared with the previous work. Better performance of steeper SS (around 72 to 80 mV/dec) and higher programming/erasing efficiency characteristics are demonstrated. Multilevel RTN characteristics are also explored with the fabricated devices.