適用於有限脈衝響應濾波器組之低面積且低能量消耗最少冗餘有號數位移與相加運算引擎

Abstract

本文提出了一種適用於有線脈衝響應濾波器的低面積且低能量消耗最少冗餘有號數位移與相加運算引擎，以滿足低功耗、靈活、低面積成本的設計考慮。所提出的架構簡化了每個乘法中的典型符號數字的數量和位移器的範圍，以減少能源消耗。然而，這個簡化卻限制了濾波器係數的使用。為了解決這個問題，本論文提出一能滿足簡化之最少冗餘有號數位移與相加運算器需求之自動化係數轉換流程。模擬的結果顯示，所提的技術可以達到近似全精確(Full Precision)乘法器運算的效能。此外，本架構具有可程式性，能適用於濾波器組中所有的濾波器。為了展現與證明所提架構的優越性，我們實現一適用於數位助聽器之10-ms, 18-頻帶, Qausi-ANSI有線脈衝響應濾波器組，並在UMC 65奈米製程下進行實作。合成的結果顯示，與利用陣列乘法器(Array Multiplier)架構相比，所提之簡化的最少冗餘有號數位移與相加運算引擎，面積可以節省34.2%，而在每筆取樣點其乘法運算中平均減少約36.9%的能量消耗。此外，由於簡化之最少冗餘有號數位移與相加運算引擎的低面積效應，在相同製程技術與相同測試條件下，我們所實作的10-ms, 18-頻帶Quasi-ANSI助聽器濾波器組比文獻中的結果減少約23.2%的功耗，而所設計之濾波器組其訊號雜訊比也能達到和全精確陣列乘法器相似的結果，符合助聽器其聽力補償演算法所需的規格。

This paper presents an area-/energy- efficient CSD shift-and-add computing engine for FIR filter to satisfy the design considerations of low power, flexible and low area cost. The proposed architecture simplifies the total number of CSD digits as well as the shift range per multiplication to reduce energy consumption. However, the simplification restricts the use of filter coefficients and a coefficient transformation flow is presented to satisfy the requirement of the proposed multiplier. The simulation result reveals this technique can recover the performance of filter and be applied for the computation of all filters in the filter bank. The filters are implemented with different reconfigurable architecture in UMC 65nm CMOS technology. According to the synthesis results, my proposed architecture is more suitable for filter bank than other reconfigurable architectures proposed in literature. The design saves the 34.2% area cost and reduces up to 36.9% energy consumption per sample when compared with conventional array multiplier. Finally, my computing engine designed for filter bank in hearing also save the 23.2% power compare with the Pre-add MAC. And the results of signal to noise ratio (SNR) of my design are similar to the results of multiplier, and all of design can meet the specification of filters. But the direct-truncated multiplier will degrade the SNR significant.