Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics

Abstract

In this paper we have studied the impacts of floating body effect, device leakage, and gate oxide tunneling leakage on the read and write-ability of a PD/SOI CMOS SRAM cell under Vt, L and W variations in sub-100 nm technology for the first time. The floating body effect is shown to degrade the read stability while improving the write-ability. On the other hand, the gate-to-body tunneling current improves the read stability while degrading the write-ability. It is also shown that the use of high-Vt and thick oxide cell transistors can improve leakage, read and write-ability without causing significant performance degradation. The test-chip is fabricated in sub-90 nm SOI technology to show the effectiveness of high-Vt and thick-oxide devices in improving stability of SRAM cells.