藉由單分子層摻雜技術形成新穎的無接面多晶矽薄膜電晶體之研究

Abstract

由於無需形成超淺接面在源/汲極上，無接面場效電晶體引起廣泛的研究興趣，更重要的是無接面場效電晶體相較於一般傳統的元件擁有更佳的短通道抑制能力。然而此種元件卻存在一個很大的議題-易於受製程浮動的影響。原因其導通路徑是原本就存在的，所以易受通道中的幾何尺寸和摻雜濃度影響，造成相對於一般傳統產生反轉層的元件擁有更大特性浮動。為此改善此缺點，我們提出在通道中漸進式摻雜所形成的改良式無接面場效電晶體去抑制製程浮動和更佳的電性表現。 此研究中，我們將會比較三種元件-反轉層場效電晶體、離子佈植無接面場效電晶體、單分子層摻雜無接面場效電晶體。在元件寬度10奈米、厚度30奈米為基礎去做模擬，我們發現通道使用漸進式摻雜相較於傳統的均勻摻雜將更容易關起我們的元件，而實驗中則發現單分子層摻雜無接面場效電晶體擁有最好的電性表現:最小的特性浮動、最低的次臨界擺幅和最高的電流開關比。更進一步探討單分子層摻雜無接面場效電晶體，我們將比較退火機制分別用快速退火爐900度30秒和微波退火2.4k瓦特600秒。用微波退火所製作的單分子層摻雜無接面場效電晶體展現出臨界電壓-0.1伏特、次臨界擺幅67mV/decade、開關電流比到7個數量級。最後，我們將特徵尺寸微縮到20奈米，單分子層摻雜無接面場效電晶體仍然有良好的電性表現。

Junctionless FETs are of great interest due to the elimination of ultra-shallow junction formation.Most importantly, Junctionless FETs has better suppression of short channel effect. However, there exists a big issue – prone to process variation on Junctionless FETs. Therefore, we proposed gradual channel doping junctionless field-effect transistor to suppress the variation and get the better electrical performance. In this study, we compared with three different kinds of devices- inversion mode FET, implant junctionlesss FET and SAM junctionless FET. In the simulation, we take device width 10nm and thickness 30nm as our base structure. We found that the gradual channel doping would close our device easier. In our experiment, We found that the novel SAM junctionless FETs show the most excellent electrical characteristics (e.g. low variation ,the well-situated Vth ,good S.S, and high on/off ratio ). The poly-Si SAM-junctionless with MWA annealing exhibit a very low threshold voltage (VTH ~-0.1V for p-type), steep with subthreshold swing (S.S. ~ 67 mV/dec) and high ION/IOFF ratio>107without hydrogen related plasma treatments. We scale the gate length down to 20nm. It still has good electrical performance.