應用於IEEE 802.11a之線性自偏壓功率放大器與變壓器結合功率放大器

Abstract

本論文討論分為兩部分，其中各部分所提出電路之晶片製作皆由TSMC 0.18μm mixed-signal/RF CMOS 1P6M製程來實現應用於IEEE 802.11a之功率放大器。 第一部分為一個採用二極體連接PMOS (Diode-connected PMOS)偏壓電路與自偏壓技術來改善功率放大器的線性度。隨著輸入功率增大，藉由二極體連接PMOS偏壓電路來增加閘極與源極間跨壓而改善線性度。整體電路提供的最高電壓為3.3V，在5.2 GHz有12.2 dB的增益，1 dB壓縮輸出功率為18.3 dBm，輸出飽和功率為22.4 dBm。在1dB點的附加功率效率為19.7 %，最高附加功率效率為27.2 %，輸出端三階互調信號為29.5 dB。以64 QAM 與54Mbps的資料傳輸率做OFDM 系統量測，在輸入功率-1 dBm下有10.7 dBm輸出功率及-25.8 dB的誤差向量幅度。 第二部分利用變壓器來結合放大器之輸出功率。變壓器閘數比設計為兩倍，以阻抗八倍的轉換來達成輸出匹配於50歐姆。整體電路提供的最高電壓為3.3V，在5.2 GHz有17.8 dB的增益，1 dB壓縮輸出功率為19.6 dBm，輸出飽和功率為24.8 dBm。在1dB點的附加功率效率為16.8 %，最高附加功率效率為31.5 %，輸出端三階互調信號為29.50 dB。以64 QAM 與54Mbps的資料傳輸率做OFDM 系統量測，在輸入功率-2 dBm下有12.8 dBm輸出功率及-25.9 dB的誤差向量幅度。

This thesis consists of two parts. All the proposed circuits were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology for IEEE 802.11a. Part I presents a linearization technique self-biased cascode power amplifier. When the RF input power increases, the diode-connected PMOS bias circuit will make the and increase to improve the linearity. The MMIC achieves a gain of 12.2 dB, and delivers a maximum output power of 22.1 dBm with 27.2 % PAE at 5.2 GHz and OP1dB is 18.3 dBm with 19.7% PAE. The OIP3 is 29.5 dB at an operation voltage of 3.3 V. The input signal which is a 64 QAM / 54Mbps OFDM modulation signal is -1 dBm, the total output power 10.7 dBm with -25.8 dB of EVM. Part II proposes a transformer combined self-biased cascode PA. It turns ratio of the transformer design in 1:2 to achieve the above impedance ratio 1:8 impedance transformation. The measured results show a gain of 17.8 dB, and delivers a maximum output power of 24.8 dBm with 31.5 % PAE at 5.2 GHz , OP1dB is 19.6 dBm with 16.8% PAE and the OIP3 is 29.0 dB with 3.3 V supply voltage. When 54 Mbps/64 QAM OFDM signal is applied, the PA delivers 12.8 dBm of average power at the EVM of -25.9 dB.