電阻式記憶體中寫入/讀取造成阻態改變錯誤之新機制

Abstract

本篇論文主要先針對在Array的排列下，氧化鎢電阻性記憶體使用Vdd/3操作方式寫入時所造成非選定元件受干擾的問題之探討，並在Set/Reset操作後量測元件受干擾的情況，接著比較元件操作前後受干擾所需時間的差別，最後量測元件在操作後，不同偏壓下受干擾所需的時間(τ)，並統計分析其密度分佈函數。 對於Array排列的RRAM而言，寫入時造成非選定元件受干擾是目前的問題之一，我們發現部分元件在短時間固定偏壓量測(CVS)時即會造成阻態的改變，這將會使元件在寫入時造成相鄰非選定元件所儲存的阻態改變。值得注意的是我們對RRAM操作數次後發現元件改變阻態所需的時間大幅縮短，但他的操作特性仍與原先相同，造成品質測試辨別的困難。同時，我們還發現不同寫入偏壓造成元件受干擾時間的密度分佈函數皆呈現高斯分布，偏壓愈高則愈容易改變阻態。

In this thesis, write disturbance on unselected cell is investigated by Vdd/3 write operation scheme in WOx-based RRAM. The difference of write failure time(τ) between pre-cycling and post-cycling is reported. The bias voltage dependence of failure time is also investigated, and the probability density function (PDF) and cumulative density function (CDF) are statistically analyzed. For RRAM memory array, write failure on unselected cell during writing is one of the most serious issues. We observed parts of device will change the resistance state during constant voltage stress(CVS), and that would disturb the unselected cell during writing the selected cell. It’s remarkable that the write failure time degrades substantially after cycling, but the operation conditions and I-V characteristics are almost the same as before, which result in the difficulty of quality test. In the meanwhile, we also observed the CDF and PDF of write failure time are well-fitted to Gaussian, and the higher the bias voltage the shorter the failure time.