完整後設資料紀錄
DC 欄位語言
dc.contributor.author呂品毅en_US
dc.contributor.authorLu, Pin-Yien_US
dc.contributor.author莊紹勳en_US
dc.date.accessioned2014-12-12T02:44:45Z-
dc.date.available2014-12-12T02:44:45Z-
dc.date.issued2014en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT070150149en_US
dc.identifier.urihttp://hdl.handle.net/11536/76076-
dc.description.abstract高介電常數材料,如二氧化鉿已經成為先進CMOS製程中閘極氧化層的主流,其原因是在原件持續不斷微縮下,由薄氧化所造成的漏電流已造成整體電路的功耗成指數增加,傳統二氧化矽或氮化矽材料已達其物理極限,也就是說必須徹底更換氧化層材料,才有辦法在不改變介電層有效厚度下把物理厚度變薄,因此,二氧化鉿應運而生。一般情況下二氧化鉿與矽間存在一層自然生成的二氧化矽,這層二氧化矽與二氧化鉿間的不完美介面會產生介面缺陷,而這些缺陷再加上氧化層中的原生缺陷會造成可靠度上嚴重問題,最明顯的影響便是臨界電壓的偏壓加溫的不穩定(BTI)現象,困難的是並不能把整層二氧化矽移除,因為那會使氧化層崩潰時間縮短,而原生缺陷也幾乎不可能完全消除,因此徹底了解這些缺陷便是非常重要的課題,其中隨機電報雜訊便是分析這些缺陷相當有用的方法。 首先,在這篇論文中我們將提出一種藉由萃取隨機電報雜訊的捕捉時間與發射時間去計算缺陷在氧化層中的位置以及能量深度,如此一來便可分析在高溫高壓下的加壓(BTI stress)會如何傷害氧化層,另外,我們藉由觀察閘極電流與隨機電報雜訊大小的比例,推出氧化層中可能的漏電路徑。而本實驗中的隨機電報雜訊將在聚積模式以及反轉模式下量測,雖然對於聚積模式下的文獻相當稀少,但我們的實驗結果顯示,唯有兩種模式並行大部分的缺陷才能完整的被記錄,而整體的分析才夠完整。 其次,從漏電路徑的啟發,我們想知道氧化層從加壓到崩潰間漏電路徑的變化情形進而得知整條崩潰路徑,方法就是藉由記錄每次加壓後缺陷產生的位置並持續加壓直到氧化層崩潰。在本實驗中,我們將會展示施以定電壓加壓(CVS)、定電流加壓(CCS)在N型金氧半電晶體以及P型金氧半電晶體的崩潰路徑,而造成這種差異的主要原因為單位時間內通過的能量通量 (Energy Flux)的不同,實驗結果顯示N型金氧半電晶體相較於P型擁有較大閘極電流但每個載子所擁有的能量較少,而定電流加壓的能量散逸會持續減少造成較多的軟性崩潰,整體來說,我們在本文中提出新的見解,崩潰路徑一共可分為兩種:紡錘型(Spindle)以及蛇型(Snake)。我們探討了崩潰路徑與CVS、CCS之間的關聯。zh_TW
dc.description.abstractHigh k materials such as Hafnium dioxide are being used as next generation CMOS gate dielectric. Conventional SiO2 or SiON dielectric has its limits in CMOS scaling: inevitable leakage current for thinner oxide. With the help of high k materials, the gate oxide now can grow thicker to reduce leakage current without increasing electrical oxide thickness. In order to achieve adequate breakdown time, a thin and native layer of SiOx is always needed. However, many well known problems need further attention: Negative Bias Temperature Instability (NBTI) due to the imperfect interface of SiOx and HfOx; Positive Bias Temperature Instability (PBTI) due to the intrinsic oxide traps. Therefore, it is important to understand the properties of these traps, and Random Telegraphic Noise (RTN) is a powerful method to analyze it. First, in this work, we have developed a method to extract the trap position and energy level by measuring the capture and emission time of RTN signals. Through these information, we can analyze the damage caused by BTI stress, in which a leakage filament was formed. Both Inversion Mode RTN and Accumulation Mode RTN will be performed after PBTI and NBTI. Although the Accumulation Mode RTN has rarely been discussed, we have also demonstrated its importance to include the measurement of accumulation mode. Our results shows, by combing Inversion Mode RTN and Accumulation Mode RTN, a comprehensive detection window can be detected. Next, from the concept of the leakage filament, it raised our great interest in finding the leakage path that leads to the final breakdown. We traced traps location after each BTI stress until breakdown, and the entire breakdown path can be revealed. In this thesis, we have performed both Constant Voltage Stress and Constant Current Stress for both nMOSFET and pMOSFET. We presented that two types of breakdown path were observed: Spindle-liked breakdown and Snaked-liked breakdown path. A new concept to explain these various results: Energy Flux. Generally, nMOSFETs have larger current but lower carrier energy compared with pMOSFETs; CCS has more progress breakdown and damage in oxide as a result of the decreasing power dispersion.en_US
dc.language.isoen_USen_US
dc.subject高介電材料zh_TW
dc.subject二氧化鉿zh_TW
dc.subject氧化層崩潰zh_TW
dc.subject隨機電報機雜訊zh_TW
dc.subjecthigh K metal gateen_US
dc.subjectCMOSen_US
dc.subjectTDDBen_US
dc.subjectRTNen_US
dc.title探討金屬高介電層互補式金氧半電晶體崩潰的新穎方法zh_TW
dc.titleA New Methodology on the Investigation of Dielectric Breakdown in High-K Metal-Gate CMOS Devicesen_US
dc.typeThesisen_US
dc.contributor.department電子工程學系 電子研究所zh_TW
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