利用非晶氧化銦鎵鋅薄膜電晶體實現低溫全氧化物積體電路

Abstract

隨著行動式電子產品的興起與摩爾定律的持續演進，系統整合面板與系統整合晶片逐漸受到重視，並將在未來成為半導體產業的新成長動力。系統整合面板或晶片除了降低成本、縮小系統體積、提升電路的等效密度與功能性之外，還可減少晶片間傳輸的延遲與功率消耗，而這些都隨著行動產品的興起而顯得日益重要。為了實現系統整合面板或系統整合晶片，簡單、低溫製程的電晶體、邏輯電路以及非揮發性記憶體都是不可或缺的項目。而寬能隙、低關閉電流、電子遷移率佳且低溫製程的非晶氧化銦鎵鋅薄膜電晶體，正是實現三者的最佳候選人。 利用非晶氧化銦鎵鋅薄膜即使在非晶相仍然不錯的電子遷移率，以及高介電係數的閘極絕緣層，我們成功的利用了全室溫的製程實現了低操作電壓的非晶氧化銦鎵鋅薄膜電晶體。其特性包括極佳的次臨界斜率 70 mV/dec、極低的臨界電壓0.4V、良好的飽和區遷移率12.6 cm^2/V．s以及良好的開關電流比10^7，非常適合於低功耗的應用。 透過非晶氧化銦鎵鋅薄膜電晶體結構與製程上的改良與接觸阻抗的減少，我們成功的實現了低操作電壓、全擺幅操作且接近理想電壓增益值的增強型主動式負載反相器。而透過空乏型非晶氧化銦鎵鋅薄膜電晶體的實現，我們成功的突破了增強型主動式負載反相器在電壓增益值上面的限制，實現了低操作電壓、全擺幅操作且電壓增益值高達40的空乏型主動式負載反相器。透過了高效能、低電壓反相器的實現，我們展現了非晶氧化銦鎵鋅薄膜電晶體在實現低溫邏輯電路的潛力。 而為了實現可應用於系統整合面板或晶片的非揮發性記憶體陣列，我們試著利用非晶氧化銦鎵鋅薄膜電晶體實現SONOS型的記憶體。透過操作機制的探討，我們提供了未來的方向與改進的目標。 利用非晶氧化銦鎵鋅薄膜電晶體，我們成功的利用了120℃以下的低溫實現了薄膜電晶體、反相器以及非揮發性SONOS型記憶體。透過三者的實現，我們可望利用非晶氧化銦鎵鋅薄膜電晶體實現低溫製程的全氧化物積體電路。低溫全氧化物積體電路將可整合進入邏輯後段製程實現系統整合晶片，或與顯示器背板製程結合實現系統整合面板，達到電路等效密度以及功能性的最大化。藉由高效能、低操作電壓、低溫製程的展現，我們相信非晶氧化銦鎵鋅薄膜電晶體在未來行動式產品應用上必佔有一席之地。

As mobile devices become ubiquitous and Moore’s Law continues driving new innovations, System-on-panel (SOP) and System-on-chip (SOC) have attracted much attention by reducing cost, shrinking the volume of IT systems, increasing circuit density and functionality, and decreasing transmission time delay and power consumption. In order to realize SOP or SOC, transistors, logic-circuit, and non-volatile memory that can be fabricated using a simple and low-temperature process are necessary. Amorphous indium gallium zinc oxide (a-InGaZnO) thin film transistor (TFT) is the best candidate for SOP and SOC because of its wide bandgap, low off-current, good electron mobility, and low-temperature process. By utilizing the high electron mobility of InGaZnO thin film even in the amorphous phase and a composite gate insulator with high dielectric constant, we successfully fabricated low-voltage and low-power a-InGaZnO TFT at room temperature. The TFT exhibits excellent electrical characteristics including a very steep subthreshold swing of 70 mV/dec, a low threshold voltage of 0.4 V, a high saturation mobility of 12.6 cm^2/V．S, and a large on/off current ratio of 10^7. Furthermore, we have successfully fabricated a low-voltage, full-swing enhancement mode-load inverter with a voltage gain close to the ideal value by improving the device structure and manufacturing process of the a-InGaZnO TFT and reducing its contact resistance. We have also successfully fabricated a low-voltage, full-swing deletion mode-load inverter with a voltage gain up to 40 which exceeds the limit of the enhancement mode-load inverter by demonstrating a depletion-mode a-InGaZnO TFT. These demonstrations of high-performance, low-voltage inverters have showed the promising potential of the a-InGaZnO TFT for logic circuits fabricated at low-temperature. In order to demonstrate high-density non-volatile memory array for SOP and SOC, we attempt to demonstrate SONOS-type memory by using the low-temperature a-InGaZnO TFT. We have studied its operation mechanism and suggested the possible direction of device improvement. We have successfully fabricated a-IGZO TFTs, inverters, and non-volatile SONOS-type memory by using a process temperature below 120℃. These results show the feasibility of low-temperature all-oxide integrated circuit by using a-InGaZnO TFTs that can be easily integrated into the logic back-end-of-line process for SOC and the display backplane process for SOP to maximize circuit density and functionality. Because of its high-performance, low operating voltage, and low process temperature, we believe that a-InGaZnO TFT will play an important role in future mobile devices.