一個可操作於0.5伏特具製程變異補償機制的動態調整電壓系統

Abstract

本篇論文提出一個可操作於0.5伏特的補償系統，此系統提供微處理器一個可調整的操作電壓，且此電壓對於微處理器所遭受到的製程變異能達到補償的效果，並希望以最低可行操作電壓讓微處理器維持正常工作，以達省功耗之目的。 此系統包含兩大部分：驗證用的數位電路以及動態調整電壓系統。驗證用的數位電路用來模擬微處理器的複雜度以及電流消耗；動態調整電壓系統則利用延遲鎖定迴路來完成，用壓控延遲線複製驗證用數位電路的關鍵路徑，將延遲時間鎖定在參考時脈的一個週期，最後藉由交換式電容穩壓電路提供可動態調整的電壓作為延遲線的延遲控制電壓，以及作為驗證用數位電路的操作電壓。 此論文使用TSMC GUTM 90nm CMOS製程實現設計，晶片佈局面積為0.718 。補償系統操作在0.5伏特，參考時脈為10MHz，交換式電容穩壓電路的輸出電壓範圍在0.15到0.45伏特之間。當製程為TT corner時，交換式電容穩壓電路的輸出電壓為0.3伏特，消耗電流為100uA，系統功率消耗為85.6uW。

This thesis proposes a 0.5V process variation compensation system. This system provides the microprocessor a rectifiable supply voltage, which can compensate the influence of process variation on the microprocessor. This system consists of two parts: a digital circuit under test (CUT) and a dynamic voltage scaling system. The digital circuit under test is used to model the complication and current consumption of the microprocessor. The dynamic voltage scaling system is realized by a delay-lock loop (DLL). The voltage controlled delay line is used to replicate the critical path of the CUT. The delay time of the critical path is locked in one clock cycle. Finally, the switched capacitor regulator is used to provide the supply voltage to the CUT and the DLL.

This chip is fabricated in TSMC GUTM 90nm CMOS technology. The total silicon area is 0.718 . The supply voltage of this compensation system is 0.5V, and reference frequency is 10MHz. The output range of the switched capacitor regulator is 0.15V~0.45V. When the system operates in TT corner, the output voltage of the switched capacitor regulator is 0.3V. The current consumption of CUT is 100uA, and the power consumption of the overall system is 85.6uW.