具梯形通道塊材鰭式場效應電晶體元件及其電路特性擾動之研究

Abstract

半導體元件技術在近幾十年來發展蓬勃，時至今日，技術節點走到16奈米，電晶體結構已由平面式電晶體轉換為立體式結構電晶體取而代之，在眾多結構中以鰭式場效應電晶體最符合成本需求及製程可行度。近來許多研究都著重在通道截面為矩形之鰭式場效應電晶體的特性探討，然而受限於製程因素，鰭式場效應電晶體大多會製程為梯形通道截面，進而對電特性造成影響。而對於元件的持續微縮，本質擾動是主要限制因素之一。因此，探討次16奈米梯形通道鰭式場效應電晶體之特性擾動已為重要課題。本論文採用三維度元件電路模擬技術，探討次16 奈米梯形通道金屬閘極暨高介電氧化層鰭式場效應電晶體 (FinFET)的本質參數擾動，此擾動包含了隨機摻雜擾動 (RDF)、線邊緣的粗糙程度 (LER)，除了元件直流特性外，亦包含電路操作時所造成的功率消耗估計。 經由模擬結果我們得知：梯形通道鰭式場效應電晶體在各種型態的線邊緣的粗糙程度下和角度相關性甚小，而各類的線邊緣粗糙程度中以由光阻定義之fin-LER和sidewall-LER對臨界電壓影響較為嚴重，由spacer製程定義的fin-LER影響最小。對於電路操作上的影響而言，較接近理想的FinFET有較佳的延遲時間，但是由於電容擾動大，導致延遲時間的擾動也較大。其中以resist-LER造成的影響最為嚴重。在隨機摻雜擾動方面，不同角度的梯型通道鰭式場效應電晶體所受的影響，在固定頂部通道寬度的情況下會隨角度減小而所受臨界電壓擾動變大，而相等通道體積與摻雜下臨界電壓擾動則約略相同，對於受限製程因素無法得到理想矩形截面通道情況下可以提供一個選擇。 綜合以上可知本研究所探討的元件擾動議題，其分析與結果對台灣半導體相關產業發展有極大的貢獻。

The technology of semiconductor device has developed fast for decades. In pursue to high performance and high packing density, the new process technology, the new devices' structures, and even the new materials play the significant roles on the complementary metal-oxide-semiconductor (CMOS) technology scaling. Nowadays, the technology node has been 16 nm. The planar MOSFET cannot provide good performance and is replaced by the multi-gate field effect transistors. Among the numerous types of multi-gate field effect transistors, the FinFET device conforms to the demands of the costs for company and the manufacturing feasibility. However, the challenges for downscaling technology node to nanoscale become more severe. Besides the limitation on lithography, the characteristic intrinsic fluctuation of devices is a restriction on device scaling. Exploring on the characteristics fluctuation of sub-16 nm FinFET devices has been an urgent priority. In this thesis, we discuss on the intrinsic fluctuation of sub-16 nm high-k/metal gate (HKMG)trapezoidal bulk FinFETs by using the experimentally calibrated 3D device and circuit simulation. The explored fluctuation issues include random dopant fluctuation (RDF),line edge roughness (LER) and process variation effect (PVE). In the analysis on RDF, we consider the two conditions of the trapezoidal FinFETs: the same top-fin width and the constant channel volume. In addition, the estimation on the power consumption from the circuit operation of trapezoidal bulk FinFETs is included. Our simulation results indicate that the influence of each type of LER on trapezoidal bulk FinFETs has weak dependence on the fin angle and the resist-LER/sidewall LER has large impact on the threshold voltage (Vth). Moreover, the modified fin patterning technology inducing LER, spacer-LER, has the least influence on the DC characteristics. For the circuit operation, nearly-ideal bulk FinFETs have better performance on delay time, however, the fluctuation is larger due to the large gate capacitance variation. Among those types of LER, the influence of resist-LER is most serious for characteristic fluctuation. For RDF on the trapezoidal bulk FinFETs with different fin angles, the Vth fluctuation is getting larger as the fin angle is getting smaller under the condition of the constant top-fin width, while the Vth fluctuation almost remains the same for each fin angle under the condition of the constant channel volume. It could provide an engineering thought on the FinFET's structure design with respect to the process limitation on fabricating the rectangle-shape FinFET.