标题: | 利用反应离子蚀刻优化多层薄膜堆叠之线宽粗糙度 Line Width Roughness Optimization of A Multiple Layer Thin Film Structure by Reactive Ion Etch |
作者: | 张竣钦 Chang,Chun-Chin 林建中 Lin,Chien-Chung 光电科技学程 |
关键字: | 线宽粗糙度;LWR |
公开日期: | 2014 |
摘要: | 为了满足传输快速、低消耗功率以及价格低廉的要求, IC电路设计的规格 , 随着时代的演进持续快速缩小。当半导体进化到一百奈米以下 (sub-100nm) , 面对的挑战与困难也就越来越多,无论是在微影、蚀刻…等方面。当尺寸越做越小时,关键尺寸 (Critical Dimension) 的控制将会是一个重要的课题,其中对于LWR (Line Width Roughness) 和 LER (Line Edge Roughness)的控制,重要性更是日渐显着。 此篇研究主要针对在底部抗反射层(Bottom Anti-Reflected Coating Layer)的薄膜堆叠中使用反应离子蚀刻机台(RIE Tool)来改善线宽粗糙度(LWR)以及关键尺寸的(Space CD)的控制。 Implementation of TiN hard mask for copper/ultra low-k interconnect is the standard technique for back end of line (BEOL) integration. Compared with the photo resist (PR) mask approach, the metal hard mask (MHM) approach has the advantages of lower stack-to-mask ratio and better etch selectivity. In addition, metal hard mask minimizes plasma induced low-k damage during low-k dual damascene etch. As device node reach 28nm and beyond, line width roughness (LWR) or line edge roughness (LER) control become a big challenge because LWR of gate directly affects Ion/Ioff property in logic devices, and affects Vth variation directly in memory devices[1-3]. In this study will put focus on different chemistry to improve LWR and control space CD with RIE tool in TiN hard mask approach. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT070158315 http://hdl.handle.net/11536/76251 |
显示于类别: | Thesis |