利用反應離子蝕刻優化多層薄膜堆疊之線寬粗糙度

Abstract

為了滿足傳輸快速、低消耗功率以及價格低廉的要求， IC電路設計的規格 ， 隨著時代的演進持續快速縮小。當半導體進化到一百奈米以下 (sub-100nm) ， 面對的挑戰與困難也就越來越多，無論是在微影、蝕刻…等方面。當尺寸越做越小時，關鍵尺寸 (Critical Dimension) 的控制將會是一個重要的課題，其中對於LWR (Line Width Roughness) 和 LER (Line Edge Roughness)的控制，重要性更是日漸顯著。 此篇研究主要針對在底部抗反射層(Bottom Anti-Reflected Coating Layer)的薄膜堆疊中使用反應離子蝕刻機台(RIE Tool)來改善線寬粗糙度(LWR)以及關鍵尺寸的(Space CD)的控制。

Implementation of TiN hard mask for copper/ultra low-k interconnect is the standard technique for back end of line (BEOL) integration. Compared with the photo resist (PR) mask approach, the metal hard mask (MHM) approach has the advantages of lower stack-to-mask ratio and better etch selectivity. In addition, metal hard mask minimizes plasma induced low-k damage during low-k dual damascene etch. As device node reach 28nm and beyond, line width roughness (LWR) or line edge roughness (LER) control become a big challenge because LWR of gate directly affects Ion/Ioff property in logic devices, and affects Vth variation directly in memory devices[1-3]. In this study will put focus on different chemistry to improve LWR and control space CD with RIE tool in TiN hard mask approach.