前瞻性嵌入式記憶體之錯誤模型與測試方法：業界實例探討

Abstract

隨著製程技術持續在微縮，晶片生產時製程管控將比以往更加難以控制。因此，越來越多的硬體缺陷和更嚴重的製程飄移在晶片中被觀察到。這些問題以不同的方式影響設計人員和測試人員。為了克服這些製程問題，電路設計人員提出了許多新的電路技術。而對於測試人員而言，這些製程的不穩定性將會影響傳統的電路行為，進而導致以往沒有被發現過的錯誤行為產生。同時，由於引用了新的電路技術，新的錯誤行為也會隨之產生。因此從測試的角度而言，將有許多接踵而來的挑戰需要被解決。 在此論文中，我們討論了不同的先進的嵌入式記憶體的測試問題，所包函的記憶體種類有嵌入式動態隨機存取記憶體 (embedded DRAM)，亞閾值操作的靜態隨機存取記憶體 (sub-threshold SRAM) 和內容可尋址記憶體（CAM）。對於每個種類的記憶體，我們首先分析了記憶體存儲單元的佈局結構來分識可能會產生的缺陷。我們使用 HSPICE 來模擬當加入可能的缺陷於記憶體存貯單元中時，其所產生的錯誤行為。接著我們歸類了所有的錯誤行為於現有的故障模型和新提出的故障模型。我們提出了有效的測試方法來涵蓋所有的故障模型。所有實驗接操作於實際的測試晶片上，實驗結果顯示所提出的測試方法是有效的。

As the technology still shrinking, the fabricated quality is much harder to control than before. Therefore, more and more hard defects and more severe process variation are observed in the silicon. These challenges influence the designers and testers in different way. To overcome these process issues, circuit designers proposed many novel circuit techniques. For the testers, these process issues will impact the traditional circuit behaviors, which will create the new fault behaviors which have never seen before. Also, the new circuit techniques may create different fault behaviors when defects occur. From the aspects of testing, there are many incoming challenges should be solved. In this thesis, we discussed the testing challenges of different advanced embedded memory macros, including embedded DRAM (eDRAM), sub-threshold SRAM, and content addressable memory (CAM). For each memory macro, we first analyzed the layout structure of the memory cell to identify the possible defects which will be occurred. We performed HSPICE simulation by injecting the possible defects into the memory cell to observe the fault behavior of each injected defect. Then we categorized the fault behaviors into the existing fault models and newly proposed fault models. We proposed effective and efficient test methods for covering all fault models. All experiments were applied on the real test chips. The experimental results show that our proposed test methods are useful.