标题: 前瞻性嵌入式记忆体之错误模型与测试方法:业界实例探讨
Fault Models and Test Methodologies for Advanced Embedded Memories: Industrial Case Study
作者: 杨皓宇
Yang, Hao-Yu
赵家佐
Chao, Chia-Tso
电子工程学系 电子研究所
关键字: 嵌入式记忆体;前瞻性记忆体;错误模型;测试方法;业界实例;Embedded memory;Advanced memory;Fault models;Test methods;Industrial case
公开日期: 2014
摘要: 随着制程技术持续在微缩,晶片生产时制程管控将比以往更加难以控制。因此,越来越多的硬体缺陷和更严重的制程飘移在晶片中被观察到。这些问题以不同的方式影响设计人员和测试人员。为了克服这些制程问题,电路设计人员提出了许多新的电路技术。而对于测试人员而言,这些制程的不稳定性将会影响传统的电路行为,进而导致以往没有被发现过的错误行为产生。同时,由于引用了新的电路技术,新的错误行为也会随之产生。因此从测试的角度而言,将有许多接踵而来的挑战需要被解决。
在此论文中,我们讨论了不同的先进的嵌入式记忆体的测试问题,所包函的记忆体种类有嵌入式动态随机存取记忆体 (embedded DRAM),亚阈值操作的静态随机存取记忆体 (sub-threshold SRAM) 和内容可寻址记忆体(CAM)。对于每个种类的记忆体,我们首先分析了记忆体存储单元的布局结构来分识可能会产生的缺陷。我们使用 HSPICE 来模拟当加入可能的缺陷于记忆体存贮单元中时,其所产生的错误行为。接着我们归类了所有的错误行为于现有的故障模型和新提出的故障模型。我们提出了有效的测试方法来涵盖所有的故障模型。所有实验接操作于实际的测试晶片上,实验结果显示所提出的测试方法是有效的。
As the technology still shrinking, the fabricated quality is much harder to control than before. Therefore, more and more hard defects and more severe process variation are observed in the silicon. These challenges influence the designers and testers in different way. To overcome these process issues, circuit designers proposed many novel circuit techniques. For the testers, these process issues will impact the traditional circuit behaviors, which will create the new fault behaviors which have never seen before. Also, the new circuit techniques may create different fault behaviors when defects occur. From the aspects of testing, there are many incoming challenges should be solved.
In this thesis, we discussed the testing challenges of different advanced embedded memory macros, including embedded DRAM (eDRAM), sub-threshold SRAM, and content addressable memory (CAM). For each memory macro, we first analyzed the layout structure of the memory cell to identify the possible defects which will be occurred. We performed HSPICE simulation by injecting the possible defects into the memory cell to observe the fault behavior of each injected defect. Then we categorized the fault behaviors into the existing fault models and newly proposed fault models. We proposed effective and efficient test methods for covering all fault models. All experiments were applied on the real test chips. The experimental results show that our proposed test methods are useful.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT079811596
http://hdl.handle.net/11536/76267
显示于类别:Thesis