適用於HEVC框內編碼之快速率失真最佳化

Abstract

在最新的影像編碼標準High Efficiency Video Coding (HEVC)中，於框內、框間中採用了相較於上一代影像編碼標準更大的預測單位大小及更多方向的預測模式，使得在率失真最佳化(Rate Distortion Optimization)中的計算複雜度大幅地提升；為了滿足即時編碼的需求，這篇論文提出了一種適用於硬體設計的快速率碼失真估測演算法，其包含率碼估測與失真估測兩種估測模型，最後此篇論文題出了相對應的硬體架構設計。 針對率碼估測，我們提出一個線性模型來提升計算速度。根據觀察經過量化後的係數絕對值較小者出現的機率遠比絕對值較大者出現的機率高，絕對值較大者出現的機率相互近似，其所產生的碼率也相似，因此我們將模型簡化為透過一個很小的查表(lookup table)方式。而失真估測則是藉由轉換矩陣維度(Transform-domain)取代原本的空間維度(Spatial-domain)，因此可以省去反離散餘弦變換(Inverse-Discrete Cosine Transform)與影像重建等部分。 在硬體設計上，採用基於4×4區塊由小而大的結構；此外，RDO採用交替式編碼排序與五級-渠道來提升硬體運算效率。我們設計的硬體若以TSMC 90nm的技術合成，大約需要50K邏輯閘的數目量，可以提供在工作頻率為270MHz的情況下，滿足處理畫面大小為4K×2K，每秒30張畫面的影片規格。

Various coding structures and modes in the latest High Efficiency Video Coding (HEVC) standard result in significant computation of rate distortion optimization to decide the best one. To fit the real time demand, this thesis proposes a hardware-friendly Rate-Distortion Estimation algorithm and its hardware design. For bit rate estimation, we propose a linear model instead of serial computation in the reference software for speedup. The model is simplified to be a small lookup table because the probability of the small values is much higher than the large values level and the probability of the large values are quite similar. For the distortion estimation, we use the transform domain instead of spatial domain estimation to save inverse transform computation. The resulted hardware design adopts with 4×4 based bottom-up structure. In addition, the RDO stage uses the interleaved coding schedule and five-stage pipeline to resolve the effect of data dependency. The hardware implementation with TSMC 90nm CMOS costs 50K logic gates which can support the processing 4K×2K 30fps video at 270MHz operation frequency.