奈米矽電晶體應變效應之研究

Abstract

本篇論文中，首先我們探討不同應變矽技術對元件的零溫度係數點(Zero-Temperature-Coefficient Points) 所造成的影響。一般來說，元件在高溫下的電流和載子遷移率會因為載子和晶格聲子散射(Phonon Scattering)的關係而降低。此外某些應變矽技術中會搭配閘極的離子佈植，這些閘極中的雜質在極薄的氧化層下會有雜質-載子散射(Impurity Scattering)效應，因此載子遷移率降低的程度會因為不同應變矽技術之間摻雜的不同而變得更為嚴重，同時實驗的結果也顯示出元件在多重閘極應變技術(Multiple-Strain Gate Engineering)下，載子遷移率變化量和溫度有強烈的相依性。因此，溫度的改變會使元件產生大量的電流偏差值。另外，我們發現元件的臨界電壓值和零溫度係數點在應變作用下的變化量大小有兩倍的關聯性，應變的作用使得矽的能隙縮窄(Bandgap Narrowing)，臨界電壓值因此降低，零溫度係數點的降低可以由伴隨著臨界電壓值的降低來解釋。根據我們的數據，多重閘極應變技術造成約200 mV的臨界電壓值的下降，多重閘極應變技術不僅只是帶來元件特性的提升，同時因為零溫度係數點伴隨著臨界電壓值的下降，減少了電路操作在零溫度係數點的功率消耗，達到低功率消耗的積體電路設計。 另外，我們藉由側壁鑲嵌技術(Sidewall Damascened Technique) 製作出一種新型鰭式薄膜電晶體(Fin-TFT)，而不需要使用先進的微影曝光機台。側壁鑲嵌技術(Sidewall Damascened Technique)利用氮化矽/二氧化矽/氮化矽的垂直三明治結構搭配濕式蝕刻，可以有效的控制鰭式通道的形狀，而不是利用反應式離子蝕刻法(Reactive Ion Etch)直接蝕刻出鰭式通道。透過控制中間的二氧化矽沉積厚度以及熱磷酸的蝕刻時間，我們可以有效地控制鰭式通道的高度和有效寬度。同時，藉由鰭式通道和源極級極同時的形成，可以有效的解決在傳統鰭式電晶體製作上串聯阻值過高的問題。另外我們將側壁鑲嵌技術(Sidewall Damascened Technique)結合無鄰近應變技術(Strain Proximity Free Technique)概念，這個概念是利用垂直堆疊的氮化矽層沒有高度(厚度)上的限制，因此較厚的氮化矽層可以對鰭式通道產生較大的應變，進一步地提升新型鰭式薄膜電晶體(Fin-TFT)的電性。 隨著我們對可撓式電子產品的需求，發展可撓式外圍集成積體電路變的日趨重要。然而在元件不斷持續地微縮下，撓曲所產生的應力對這些尺度在奈米等級元件的影響卻很少被探討。在這份研究中，我們將對直徑約10奈米的環繞式閘極奈米線通道電晶體施加外部應力，進一步探討外加應力對奈米線通道電晶體的影響。實驗的研究結果顯示，外加應力仍舊會對奈米線通道電晶體造成應變，進而改變奈米線通道電晶體的電特性，實驗中我們觀察到臨界電壓(Threshold Voltage)下降、轉移電導(Transconductance)增加以及電流增加，這些結果顯示外加應力會對載子傳輸通道產生應變，造成元件載子遷移率的改變，進而產生電性上的變化。

The impact of strain effect on Zero-Temperature-Coefficient (ZTC) points of devices with various strain engineering technologies is presented in this dissertation. The degree of mobility reduction becomes severe on devices with multiple-strain gate engineering. The reduction of mobility becomes severe as a result of impurity scattering which results from gate implantation impurities. Experimental results show stronger temperature dependence of the shift in the mobility which results in larger current deviation for devices with multiple-strain gate engineering. A strong correlation between VG(ZTC) and threshold voltage is found. The shift of VG(ZTC) doubles that of threshold voltage. The ZTC point decreased under multiple-strain gate engineering can be explained by the decreased VTh. According to our data, thanks to the multiple-strain gate engineering, the shifts in VTh are larger (~200 mV) than that caused by traditional strain engineering. Multiple-strain gate engineering brings not only improvement of performance but lower the VG(ZTC). Circuit operated at lower VG(ZTC) has great benefit for consideration of power consumption. In addition, we proposed a novel fin-like polycrystalline silicon thin-film transistor by alternatively innovative process, named Sidewall Damascened Technique without any advanced lithography tool. The alternatively innovative process employs the advantage of etching selectivity in nitride/oxide/nitride sandwich layers. The fin shape can be controlled well by wet etching process instead of Reactive-Ion Etching (RIE) process. The fin height can be controlled effectively by thickness of oxide deposition and the fin width can be controlled by sidewall cavity formation and hot phosphoric acid process as well. In addition, the high source/drain resistance can be significant reduced by formation of fin body and raised source/drain simultaneously. The Strain Proximity Free Technique (SPFT) combined with Sidewall Damascened Technique proposed can further improve the performance of Fin-TFTs. The strain resulted from top nitride and bottom nitride of nitride/oxide/nitride sandwich layers can avoid limitation of the stressor volume of deeply scaled FinFETs on account of vertically stacked structure. With the demand for flexible consumer electronics, flexible peripheral circuits are needed. However, the impact of mechanical stress on extremely small scale device, such as sub-10-nm GAA nanowire FETs has been rarely addressed in the reports. The characterization of strained Gate-All-Around Sidewall Damascened Nanowires-FETs (GAA SWDNW-FETs) is presented in this dissertation as well. The dimensions of the poly-Si NWs are approximately 7 nm × 12 nm with a smooth elliptical shape. According to our results, strained silicon is useful even in a sub-10 nm poly-Si nanowire device. A significant performance improvement by biaxial tensile strain 0.05% and 0.07% is observed, including the threshold voltage VTh reduction ~ –37 mV and -56 mV, maximum of transconductance ~ +23% and +50% and driving current ID enhancement ~ +30% and +40%. The larger shift in threshold voltage and improvement in drain current of longer nanowires indicates that they have greater stain in their suspended structures.