十億級資料傳輸室內無線 SC/OFDM 接收器之系統架構設計與相位雜訊消除演算法及設計

Abstract

為了處理應用於60 GHz通訊系統之高頻元件的相位雜訊 (phase noise)對系統位元錯誤率造成的影響，這篇論文提出可支援雙模式、低複雜度並可達到IEEE 802.15.3c規格要求的相位雜訊消除演算法及硬體設計。同時，因其運算複雜度低之故，能夠以硬體實現並使用於通訊系統晶片。本無線基頻接收機之相位雜訊消除演算法在OFDM的模式上，以一頻域演算法在頻域消除共同相位差，並利用迴授電路，以長期追蹤載波頻率飄移的影響。而針對SC模式之兩階段相位雜訊消除演算法其90%以上的硬體能與OFDM模式之頻域演算法共用。 除此之外，本論文優化針對IEEE 802.15.3c標準設計與實作之正交分頻多工(orthogonal frequency division multiplexing (OFDM))和單載波 (single carrier (SC))兩種模式之無線基頻接收機。本無線基頻接收機一共包括五個主要功能性電路區塊，分別是前置碼/符元邊界偵測，取樣時脈飄移同步估測補償，載波頻率飄移同步估測補償，頻域等化器以及相位雜訊消除。本論文將關鍵之模組為兩種模式共用已達到節省硬體以及降低功率消耗之目的。 整體無線基頻接收器系統電路以8倍平行架構操作頻率為500MHz，資料傳輸率在SC和OFDM模式中，分別可達到16 Gb/s和24 Gb/s。硬體面積共203萬個等效邏輯閘，總功耗為297毫瓦。在非直視通道環境下，訊雜比為12分貝(dB)的情況下，也在未具有編碼保護下的位元錯誤率在SC和OFDM模式中，分別可達到 3.09×〖10〗^(-5)和1.21×〖10〗^(-3)。

In order to deal with the phase noise caused by the RF device which are required for 60GHz communication system might degrade the system performance. This thesis proposes a dual mode, low complexity and also achieves the specifications of the IEEE 802.15.3c standard phase noise cancellation (PNC) algorithm and hardware design. Meanwhile, its low complexity allows the implementation of baseband receiver. While in OFDM mode, a frequency domain algorithm for common phase error (CPE) cancellation and a feedback loop for long term residual carrier frequency offset tracking is provided in baseband receiver. As for SC mode, a two-stage phase noise cancellation algorithm is proposed and 99.8% of the hardware can be shared with the frequency domain algorithm for HSI mode. Besides, this thesis improves a single carrier (SC) mode and orthogonal frequency division multiplexing (OFDM) mode dual mode wireless receiver which is designed and implemented for IEEE 802.15.3c standard. There are five main functional blocks in the baseband receiver, which are boundary detection, sampling clock offset (SCO) cancellation, carrier frequency offset (CFO) cancellation, frequency domain equalizer, and phase noise cancellation. The hardware of key module between SC/OFDM modes are shared to reduce the hardware cost and power consumption. The baseband receiver works at 500MHz with 8X-parallelism architecture. The data rate can achieve 16 Gb/s and 24 Gb/s in SC mode and HSI mode, respectively. The area is 203 K gate count and the power is 297 mW. In NLOS channel, the un-coded BER at SNR 12dB can achieve 3.09×〖10〗^(-5) and 1.21×〖10〗^(-3)in SC mode and HSI mode, respectively.