一個應用於4G LTE-A的非整數鎖相迴路

Abstract

本論文提出一非數鎖相迴路，可作為第四代行動通信-進階長期演進技術通信協定(4G LTE-A)中收發器地方頻率的產生器。LTE-A系統採用載波聚合技術，能大幅提升無線傳輸效能，根據2013年3GPP公佈的文件[1]，載波頻率的頻率規格為 699~3800 (MHz); 其通道頻寬共有五種，分佈於1.4~20 (MHz)之間。如此寬廣的頻帶及複雜的頻寬條件皆使得頻率合成器不易設計。傳統的寬頻非整數鎖相迴路常使用多振盪器或多混波器來提升輸出頻率範圍，大幅增加系統的複雜度。針對此應用，本論文使用一單迴路鎖相迴路，其中包含一變壓器基準振盪器來達成寬頻輸出的需求，並且採用相位內差的機制降低量化誤差雜訊。震盪器的頻率輸出範圍為5.592 (GHz)~10.76(GHz)，經由除頻後可得到目標頻率同時提供IQ相位; 此外，透過擾亂相位內差可達到100(KHz)的頻率解析度。此晶片使用台積電九十奈米互補式金氧半導體製程，核心電路在振盪器操作在10.76 (GHz)時消耗 33.23 毫瓦，操作在 1.2 伏特電壓，晶片核心電路面積為1.352平方毫米。

This paper describe a fractional-N PLL expected to provide LOs in transceiver of LTE-A. LTE-A system adopts carrier aggregation technique to improve quality of ser-vice (QoS) by using multiple fractional band at the same time. According to E-URTA band[1] released in 2013, specifications of LOs are from 699 to 3800 (MHz) and 1.4 to 20 (MHz) for frequency range and transmission bandwidth, respectively. Wide opera-tion range and complexity of bandwidth are challenges for PLLs. Conventional wide-band fractional-N PLLs typically have complex architectures, such multiple VCOs and multiple mixers, to increase output frequency range. In this thesis, a single loop PLL composed of a wide-band VCO and fractional divider is designed for proposed ap-plication. Transformer-based VCO is used for wide tuning range, and phase-interpolation technique is adopted to reduce quantization noise in fractional mode. Proposed VCO covers from 5.592 to 10.76 (GHz), and SPEC of frequency range obtained by adding cascade dividers after VCO directly. Resolution is 100 (kHz) achieved by dithering phase interpolator. This work fabricated in 65 nm CMOS tech-nology, the circuit consumes 33.23 (mW) without output buffer when VCO operated at 10.76 (GHz), from 1.2V supply with a core area of 1.352 (mm2).