真實處理器之高能源效率任務內動態電壓調整策略

Abstract

這幾年來，個人隨身助理與手機等手持裝置需要運算能力強大的處理器來快速地處理各種多媒體應用。然而越快速的處理器所消耗的能源也越高。如果將處理器一直維持在最高速度來執行所有的工作，會造成能源的浪費。動態電壓調整演算法可以依據處理器的實際工作量，動態調整其頻率與電壓來達到省電的目的，而一個好的演算法必須也能滿足即時性工作的時間限制。本篇論文有兩個主要貢獻：第一，相對於PACE [2]複雜的推導，在任務內動態電壓調整模型下，我們利用朗冠吉係數法很簡潔地導出消耗最少能源的最佳速度排程。第二，PACE假設處理器模型是理想的，也就是說這種處理器能支援各種的頻率以及相對應的電壓。我們稱這種處理器為理想處理器。事實上，一般處理器只能提供有限的頻率及電壓組合，相對於理想處理器，我們稱這種處理器為真實處理器。因為能源消耗並不是簡單的頻率函數，將原本的非線性規劃問題轉換成多重選擇背包問題是比較合理的。我們利用動態規劃法導出在真實處理器上消耗最少能源的最佳速度排程。分析結果顯示，相較於PACE，我們的演算法平均節省了三倍真實處理器的能源。

In recent years, hand-held devices such as personal digital assistants (PDAs) and cell phones require powerful CPUs to handle a variety of multimedia applications as fast as possible. However, the faster the CPU speed, the higher the CPU energy consumption. It is not energy efficient to run a CPU in full speed all the time for all kinds of tasks. A dynamic voltage scaling (DVS) algorithm can adjust CPU frequency/voltage dynamically depending on CPU workloads to save energy, and a graceful DVS algorithm must meet the time constraint of each real time task. There are two main contributions in this thesis. First, unlike the tedious derivation in PACE [2], we have derived an optimal speed schedule with minimal energy consumption in the intra-task DVS model in an elegantly way by using the Lagrange multiplier procedure. Secondly, the CPU model assumed in PACE is ideal, meaning that the CPU supports all kinds of frequencies and corresponding voltages. We call such CPUs as ideal CPUs. In reality, CPUs only support a limited set of frequency/voltage levels, and we call this kind of CPUs as realistic CPUs in contrast to ideal CPUs. Since energy consumption is not a simple function of frequency, it is more reasonable to transform the original nonlinear programming problem to a multiple-choice knapsack problem (MKP) [35]. We use dynamic programming to derive an Optimal Schedule for Realistic CPUs (OSRC) with minimal energy consumption. Analysis results have shown that the energy saving of the proposed OSRC is three times in average better than that of PACE in realistic CPUs.