精準多相位時脈產生技術

Abstract

多相位時脈常被應用在時序還原電路、相位/頻率調變電路與時序交錯電路中。這些電路的效能主要被多相位時脈的解析度所決定。換句話說，多相位時脈的數量與精確度決定了系統效能。這是由於這些相位皆被利用來控制資料處理的程序。隨著應用頻率的增加，資料處理的時間週期會相對地縮小。若此時電路發生了不匹配的現象，則時脈訊號的時間邊界將會因而減小，造成資料處理的困難度。在製程技術的不斷演進之下，電路不匹配的情形將會因電路元件的縮小更加的嚴重。

本篇論文描述一種使用電阻串列與電阻環圈以達成相位平均化與相位內插目的之多相位時脈產生技術。相位平均化可以降低相位誤差，而相位內插可以增加可取用的相位數量。除了波型因素之外，相位平均化與相位內插的效能是被相位平均化電路的時間常數規格化後之時脈頻率所決定。為了獲得更高的相位精確度，該相位平均化電路需要較小的時間常數。若系統可以產生出精確地且多相位的時脈訊號，則可以利用褶疊器去產生倍頻的時脈訊號。為了驗證電阻環圈的相位平均化與相位內插能力，本論文設計了一個使用標準 0.35um 互補金屬氧化物半導體製程技術的數位對相位轉換器。量測結果顯示，此應用了相位平均化與相位內差技術的數位對相位轉換器可以達到八位元的解析度。

使用預先充電式延遲單元以調整時脈產生器輸出相位之延遲時間的電路技術也將於本論文內闡述。其延遲時間調整機制是藉由改變該延遲單元內部端點的充放電行為而產生。該機制於各種不同的條件之下的線性度將會被詳述。該延遲單元需要使用數位對類比轉換器以產生預先充電之電壓準位，且需要組合式邏輯閘以由時脈產生器之輸出產生時序控制訊號。為了驗證該延遲單元之功能，本論文設計了一個使用標準 0.18um 互補金屬氧化物半導體製程技術的鎖相迴路。量測結果顯示，該延遲單元具有 0.145psec 的解析度，且整體可控制延遲時間範圍為 69.78psec。

Multi-phase clocks can be found in applications such as timing recovery, phase/frequency modulation and demodulation, and time-interleaved applications. The performance of those systems is mainly determined by the resolution of the available clock phases, i.e., how many and how accurate the available phases are, because all of the output phases of multi-phase clock generators will connect to outer parts for controlling the procedure of data processing. With the increasing of the applied processing frequency, the period of data processing is getting shorter and shorter. Also, if the circuits in the clock generators do not match with outer environment and inner status, the timing margin of the clock signals will get much narrower to raise the complexity of the data processing terribly. Furthermore, with the ongoing advance of fabrication process, the problem of circuit mismatch will be getting worse and worse because of the circuit element's shrinkage.

This thesis described circuit techniques using resistor strings (R-strings) and resistor rings (R-rings) for phase averaging and interpolation. Phase averaging can reduce phase errors, and phase interpolation can increase the number of available phases. In addition to the waveform shape, the averaging and the interpolation performances of the R-string and R-rings are determined by the clock frequency normalized by a RC time constant of the circuits. To attain better phase accuracy, a smaller RC time constant is required, but at the expense of larger power dissipation. If multiple-phase clocks are available, folders can be used for frequency multiplication. To demonstrate the resistor ring's capability of phase averaging and interpolation, an 8b 125MHz digital-to-phase converter (DPC) was designed and fabricated using a standard 0.35um SPQM CMOS technology. Measurement results show that the DPC attains 8-bit resolution using the proposed phase averaging and interpolation technique.

Circuit techniques using variable pre-charged delay units (VPDUs) for adjusting the time delay of the output phases of clock generators are also described in this thesis. The delay tuning mechanism is realized by changing the charging and discharging behavior at the internal node in VPDUs. The linearity of delay tuning in different conditions is described. VPDUs require digital-to-analog converters for providing pre-charging voltages, and combinational logic gates for generating timing control signals from clock generator outputs. To demonstrate the VPDU's capability, an 8-channels 1GHz phase-locked loop was fabricated using a standard 0.18um CMOS technology. The digitally-controlled VPDU has a 0.145psec delay control resolution and a total control range of 69.78psec.