邏輯90奈米技術節點淺溝渠隔離機械應力效應 對於設計相關之MOS電性所造成的影響

Abstract

在次90奈米元件技術節點上，淺溝渠隔離(STI)之使用已變的更具挑戰性了，其中一個主要的挑戰是來自於隨著STI之縮小而要處理STI製程所導致的機械應力對MOSFET之電性所造成的影響。 在此論文中，我們將藉由一組完整的不同尺寸大小設計之主動區(active area)的實驗，在先進的90奈米CMOS製程上，有系統地探討STI導致之機械應力對MOSFET電性所造成之影響。並且亦報告了驅動電流(drive current)，關態電流(Off current)及臨界電壓(threshold voltage)對多晶矽閘極到STI間之距離的關係，在STI應力的作用下，觀察到NMOS與PMOS有著相反的特性趨勢且對於不同尺寸大小設計的通道寬度(W)與長度(L)對STI應力之敏感度亦有所不同。此外，我們也在隨著不同大小的主動區與STI設計作定性的應力分佈模擬，以更了解應力變化之趨勢，藉以驗證應力相關的矽電特性現象的描述。特別的是被氧化矽包圍的矽元件會顯示出壓縮態應力(compressive stress)，且它會隨著元件縮小而變大。因此在此研究中，我們證明在90奈米與次90奈米元件技術節點上，STI應力在IC設計的階段中能夠也必須被考量進去。

At sub-90nm device nodes, implementation of shallow trench isolation (STI) becomes more challenging. One of the major challenges with scaling STI have to deal with is the STI-induced mechanical stress effect which impact MOSFET electrical behavior.

In this thesis, impact of shallow trench isolation (STI) induced mechanical stress on MOSFET electrical properties was investigated systematically by means of a full-matrix active area layout experiment in advanced 90nm CMOS process technology. Both the drive current, off current and threshold voltage variations as a function of the poly to STI distance are reported. From this experiment, an opposite trend is observed between n- and p-MOS with the presence of STI stress and transistor layout with different size of W and L has different sensitivity to STI stress. In addition, simulation of stress distribution with various active and STI dimensions was performed qualitatively for analyzing the stress trend in detail to verify the silicon electrical characterization of stress-dependent phenomenon. In particular, silicon device surrounded by silicon oxide exhibits compressive stress, which will be higher as the device dimension becomes smaller. Therefore, from this study, we demonstrate that stress effects can and should be taken into account in IC design phase in present and sub 90nm nodes CMOS generations.