低介電阻障層All-in-one蝕刻在銅雙鑲嵌製程的特性研究

Abstract

在深次微米的半導體製程中，導線的信號傳輸延遲效應，嚴重影響電子元件的表現。為了減輕這個問題，業界普遍採用以下兩個方式。首先是以低電阻的銅導線取代傳統的鋁導線；另外，則是選用低介電常數的材料供金屬介電層使用，但這兩種方式都在製程的整合上遇到許多問題。若採用低介電常數的材料而無中間蝕刻終止層，雙鑲嵌製程在蝕刻深度的控制、蝕刻輪廓、條紋及琢面等方面都將遇到很大的挑戰。工程師們企圖以製程整合的方式，在降低生產成本及簡化生產流程的同時，兼顧元件的電性表現。進而發展出all-in-one的製程技術，以滿足低成本、高產出的要求。 All-in-one技術在同一個清潔模式的腔體中，整合了溝槽蝕刻、去光阻及阻障層去除等步驟。這個方式也同時解決了一些阻障層去除步驟之後的製程問題。本篇論文提供的實驗結果，是關於在去光阻及阻障層去除的製程整合所遇到的問題，包括銅氧化物引起的損害銅導致電性失效、 損害銅與銅質阻障種晶層過差的附著力。為了減少損害銅導致的失效並提供更好的解決方案，可以藉著考慮整合製程步驟以及修改製程程式。實驗的程序主要是藉著兩個階段，包括控擋晶圓以及圖案晶圓的實驗; 接著是電性晶圓的實驗。這裡將討論一些不同氣體組合的製程趨勢及蝕刻後處理的步驟，進而驗證這個製程方式是有效的。

In the era of deep submicron semiconductor fabrication, interconnection resistance-capacitance (RC) time delay dominates the performance of whole integrated circuits (ICs). To mitigate the issue, two realistic methods are accepted popularly. The first method is to replace the aluminum wires with copper interconnects which offer lower resistivity. The second method is to use a lower dielectric constant material as the inter-metal dielectric (IMD). However, the integration of such material has encounter enormous problem in mass production. When the low-k material without middle stop layer was introduced, the dual damascene processes present unique challenges of etch depth control, etch profile, striation and faceting. As a result, people struggled to align an integrated process flow to reduce the cost of production and to simplify the process flow without any impact on chip performance. Therefore , the all-in-one process was developed to meet low cost and high productivity requirement. The all-in-one process was integrated trench etch step , strip step and barrier removal step into only one clean mode chamber. Meanwhile, some process issue after barrier removal step will also be solved. This paper will present experimental results of the process development that had been carried out for trench etch with integrated strip and barrier removal process and some various issues, like copper damage by oxidized copper residue leading to electrical failure , poor adhesion between damaged surface and barrier seed layer . To reduce the copper damage induced failures and provide the better solution, recipes can be modified and the process step procedures are considered. The experiment procedures will mainly be finished by two phases. First , there are some tests for blanket wafers results and physical results. Secondary, the experiment will optimize process on electric test to meet the process acceptable specifications. Then some process trends will be discussed by different gas combinations and some post etch treatment then prove the process approach is evaluated to be workable.