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dc.contributor.author郭俊延en_US
dc.contributor.authorJyun-Yan Kuoen_US
dc.contributor.author蘇彬en_US
dc.contributor.authorPin Suen_US
dc.date.accessioned2014-12-12T02:51:34Z-
dc.date.available2014-12-12T02:51:34Z-
dc.date.issued2006en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT009311528en_US
dc.identifier.urihttp://hdl.handle.net/11536/77999-
dc.description.abstract本論文探討單軸應變對金氧半電晶體特性的影響,採用的研究方法是比較共同製程製造的無應變元件與應變元件。從萃取出的本質汲極電流,我們發現飽和區汲極電流的提升因為載子速度飽合效應而較線性區汲極電流的提升小,這表示應變元件會有比無應變元件小的飽和電場與飽和電壓,這個推測我們已從輸出電阻對汲極電壓特性圖萃取出的飽和電壓得到驗證。較小的飽和電壓使應變元件的gm/Id值在大閘極電壓下小於無應變元件的gm/Id值。 然而當閘極電壓較小時,應變元件的gm/Id值卻比無應變元件的gm/Id值大。這是因為在閘極電壓較小時,載子的遷移率是決定於庫倫散射,而流動載子的屏蔽效應使載子遷移率隨閘極電壓增加而增加,又應變元件具有較大的遷移率對閘極電壓敏感度,導致應變元件的gm/Id值較大。 P型應變元件的輸出阻抗明顯比P型無應變元件的輸出阻抗小。輸出阻抗是取決於汲極引發的能帶降低效應,可以用1/(gm×|dVth/dVd|)表示,P型應變元件的輸出阻抗變小主要是因為明顯提升的gm。 P型應變元件的dc增益(gm×Rout)稍微較P型無應變元件的dc增益小。元件的dc增益可以用1/(|dVth/dVd|)表示。P型應變元件的汲極電阻較小,導致臨界電壓對汲極電壓敏感度變大而使dc增益變小。N型應變元件的dc增益稍微較N型無應變元件的dc增益大,可能原因是N型應變元件的基極/汲極內建電位因為應變而變小,導致臨界電壓對汲極電壓敏感度變小。 本論文希望能提供類比設計師在使用先進應變元件時,對先進應變元件的類比特性有更多的了解。zh_TW
dc.description.abstractThis thesis investigates the impact of process-induced uniaxial strain on MOS-FET performance by comparing the co-processed unstrained and strained devices. The extracted intrinsic Id,sat enhancement is smaller than the Id,lin enhancement due to ve-locity saturation. The smaller Id,sat enhancement indicates a smaller Esat and Vdsat, which is verified by the extracted Vdsat using the Rout vs. Vd characteristics. The re-duced Esat is responsible for the degraded gm/Id for our strained PFET in the high Vg regime. In the low Vg regime, however, the gm/Id for the strained PFET is significantly higher than the control device. This is because in the low Vg region, the mobility is mainly determined by Coulombic scattering. The mobile carrier screening makes μeff increase with Vg. The larger dμeff/dVg for the strained device is responsible for the higher gm/Id. The Rout for the strained PFET is significantly reduced. The Rout in high Vd re-gion is determined by drain induced barrier lowering and can be modeled by 1/(gm×dVth/dVd). The reduction in Rout for the strained device is mainly due to the en-hanced gm. The dc gain(gm×Rout) for the strained PFET is slightly less than its control coun-terpart. This is because the strained device has a smaller Rsd and hence a higher Vd sensitivity of the threshold voltage. For the strained NFET, The dc gain is slightly lar-ger than its control counterpart due to the reduced drain/body build-in potential. This work may provide insights for analog design using advanced strained de-vices.en_US
dc.language.isoen_USen_US
dc.subject單軸應變金氧半場效電晶體zh_TW
dc.subject類比特性zh_TW
dc.subject數位特性zh_TW
dc.subjectuniaxial stained MOSFETen_US
dc.subjectanalog performanceen_US
dc.subjectdigitial performanceen_US
dc.title單軸應變金氧半電晶體的特性分析zh_TW
dc.titlePerformance Dissection of Uniaxial Strained MOSFETs for Digital/Analog Applicationsen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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