具倒T型閘極之多晶矽奈米線通道薄膜電晶體與氮化矽記憶體元件之製作與特性分析

Abstract

在本篇碩士論文中，我們利用簡易的邊襯蝕刻技術製作出一種具有多閘極結構的多晶矽奈米線薄膜電晶體。藉由小體積的奈米線通道對外在電壓敏感度高的特性，還有倒T型閘極的使用，可以獲得較佳的閘極控制能力，進而增進元件的性能。除此之外，由於強烈的閘極耦合效應，在分離的上閘極加上適當的偏壓，便可精確地調控臨限電壓。 基於此獨特的獨立雙閘極奈米線電晶體結構，我們也製作了具有奈米線通道的TFT-SONOS記憶體元件。其中元件的兩個閘極分別作為寫入閘和臨限電壓調控閘，提供更富彈性的寫入與讀取操作。本篇論文中，我們研究並探討了其基本電性與寫入/抹除特性，此外，我們也發現在上閘極加入適當的偏壓，可以有效增加寫入的效率，進而獲得較寬的感測區間。

In this thesis, a poly-Si nanowire TFT device with multiple-gated configuration was fabricated by utilizing a simple and low-cost spacer etching technique. With the aid of strong coupling effect between the inverse-T gate and the top gate due to the tiny body of the NW channels, the electrical characteristics are greatly enhanced. In addition, the threshold voltage is capable of being finely tuned with a proper gate bias. Based on this unique independent double-gate structure, NW TFT-SONOS memory devices were also fabricated and characterized. The two gates which function as programming gate and threshold voltage adjusting gate, respectively, provide flexibility for programming and reading operations. The electrical characteristics including program/erase properties were also studied. Additionally, adding an adequate top-gate bias is found to improve the programming efficiency, resulting in larger memory window.