具有奈米線通道的多晶矽薄膜電晶體之特性改善

Abstract

在本論文中，我們研製一種新型奈米線薄膜電晶體，並使用兩種方法來降低在該新型奈米線薄膜電晶體的漏電流。第一種方法是在頂部的閘極與汲極交疊區域中，閘極與氧化層之間，加入一層額外的氮化矽，藉此降低閘極/氧化層交界處的電場強度，以有效減少閘引致汲極漏電流(GIDL)漏電流。第二種方法則是加入快速升溫退火製程來改善晶體的特性，藉此降低缺陷對漏電流的貢獻。由研究中結果來看，兩種方法均為有效。 此外，針對奈米線通道品質的改進，我們也使用金屬誘導側向結晶(MILC)的方式來加以改善，並藉此大幅提昇奈米線薄膜電晶體的特性。由電子顯微鏡分析的結果發現，沿著電晶體通道方向有大的針狀形的晶體結構，使得通道有類似單晶體的結構與特性，因此元件的電特性包含載子遷移率、次臨界擺幅等可得到明顯的改善。此外，在本研究中也比較了不同位置的成核開口配置對元件特性的影響。

In this study, a novel nanowire (NW) transistor was fabricated and characterized. Two methods were explored to reduce leakage current of the newly-proposed nanowire devices. One is to insert a Si3N4 layer in between the gate oxide and gate in the top gate-to-drain overlap region to effectively reduce the strength of electrical field and thus the magnitude of the gate-induced drain leakage (GIDL). The other scheme is to apply an additional RTA step to improve the film quality. Both methods are shown to be effective in this regard. MILC method was also employed to improve the channel film crystallinity and the characteristics of NW-TFTs. Transmission electron microscopy (TEM) characterization indicates that the needle-like grain with crystallization direction along the NW channel is resulted, and leads to a single-crystal-like structure as the lateral size of the grain approach to the NW dimensions. Electrical characteristics including carrier mobility and subthreshold swing were dramatically improved with this approach. The impact of seeding window arrangements were also explored in this study.