多層閘極介電層之奈米尺度薄膜電晶體之研究

Abstract

在此論文中，我們首先提出了多層閘極介電質結合奈米線多通道的薄膜電晶體之結構，此結構具有高性能薄膜電晶體的特性，另一方面，也同時具有非揮發性記憶體的特性。 在薄膜電晶體方面，我們利用ONO多層閘極介電質來調配閘極介電質的介電常數，在不減少薄膜厚度的情況下，提高閘極的控制能力；另一方面，我們同時利用奈米線在邊緣處的曲率半徑較小，在相同電壓下，有較大的電場之特性，製作出多通道奈米線的薄膜電晶體，可以有效的降低導通電壓(threshold voltage)，增加開關電流比(On/Off ratio)，較陡峭的次臨界導通斜率(subthreshold slope)，和更優良的元件驅動能力，其電性較一般標準結構的薄膜電晶體為好。 在非揮發性記憶體方面，由於奈米線在邊緣處具有較大的電場，可以使元件在進行寫入/抹除(Program/Erase)的操作時，具有較高的效率，另一方面，奈米線結構的非揮發性記憶體，無論是在資料的保存性(Reliability)方面，或是多次讀寫(Endurance)方面，都具較好的元件可靠度。 多層閘極奈米線薄膜電晶體有極大的潛力應用在面版上的系統整合，利用多層閘極介電質薄膜電晶體同時具有高效能驅動元件及非揮發性記憶體元件的特性，可以大幅的簡化製程步驟。

In this thesis, we have proposed and fabricated the SONOS-TFT with nanowire structure. The SONOS-TFTs can be used on the high performance driving device application and nonvolatile memory device application. For driving device application, we have used multilayer ONO gate dielectrics to make change the effective dielectric constant. The proposed TFT with ONO gate dielectrics have better gate control ability. On the other hand, nanowire has larger electric-field in the corner region at the same voltage. The SONOS-TFT with multiple nanowire channels have superior electrical characteristic, such as lower threshold voltage, higher On/Off ratio, steeper subthreshold slope, and superior driving ability. In nonvolatile memory application, the SONOS-TFT with nanowire structure have superior program / erase efficiency for its higher electric field near the corner region. On the other hand, SONOS-TFT with nanowire structure have better reliability, either retention or endurance. The SONOS-TFTs combined the TFT and memory properties at the same time. Furthermore, the process flow is compatible with conventional poly-Si TFTs fabrication without additional process steps. Hence, the application of SONOS TFTs structure can reach the goal of system on panel (SOP) in the future.