二氧化鉿堆疊式閘極在n型金氧半場效電晶體上的特性研究

Abstract

隨著尺寸的微縮，當傳統的二氧化矽厚度縮到1到1.5奈米，大量的漏電流將會從介電層直接穿隧過去，因此利用高介電常數介電質來取代傳統的二氧化矽是必要的。由於高介電常數介電質在相同等效厚度下，有較厚的實際介電層，可用來抵擋大量的漏直接穿隧電流。然而，在高介電常數中所產生的遷移率衰減與臨界電壓漂移都是主要的存在問題。所以提昇遷移率並且了解高介電常數導致可靠度的問題都是在本研究中，探討的重點。 本文中，我們先探討具有氮化矽覆蓋層之二氧化鉿堆疊式閘極N型金氧半場效電晶體 (nMOSFETs) 特性。其中，使用電漿增強式化學氣相沉積之氮化矽層，可以提供通道區域內的伸張應力。由於通道內的伸張應力增強，N型金氧半場效電晶體之驅動電流隨著氮化矽層厚度增加而增大。同時，我們也探討，具伸張應變通道的金氧半場效電晶體，其定電壓應力與熱載子注入可靠度特性分析，與在定電壓應力之後低頻雜訊分析。雖然較厚氮化矽覆蓋層可以增大N型金氧半場效電晶體的驅動電流，但定電壓應力、熱載子注入效應與定電壓應力之後低頻雜訊分析卻在較厚覆蓋氮化矽之電晶體更為嚴重。特別是在較高電壓下，氮化矽層造成的區域應力導致較多的介面狀態產生，這可能是由於通道內的應變能量造成大量矽氫鍵結斷裂。而覆蓋氮化矽之N型金氧半場效電晶體， 在定電壓應力與熱載子注入比較之下，我們觀察到熱載子注入有較小的臨界電壓的偏移與界面狀態密度改變，這表示在二氧化鉿堆疊式閘極N型金氧半場效電晶體中，定電壓應力造成的可靠度衰減相較於熱載子注入有顯著嚴重趨勢。

As the conventional SiO2-based gate insulator scales down to 1.0nm-1.5nm, a large direct tunneling leakage current generates through ultra-thin oxide. Utilizing high-k dielectric to replace SiO2-based gate as an insulator to eliminate high leakage current is necessary due to its larger physical thickness under the same electrical thickness. However, mobility degradation and threshold voltage instability are the biggest concern. Therefore, enhance mobility while keeping low leakage current is our aim to realize. Besides, the reliability discussion for high-k dielectrics needs to be understood. In this thesis, nMOSFETs devices were carried out with capping SiN layer on HfO2/SiON gate stack. The SiN film deposited by PECVD was used to induce tensile strain locally in the channel region. Driving currents on nMOSFETs devices are enhanced as the thickness of SiN layer increases due to increasing tensile strain in the channel region. Constant voltage stress (CVS) and hot carrier injection (HCI) characteristics of nMOSFETs with tensile strain in the channel are discussed. Flicker noises are also measured after CVS. Although nMOSFETs devices with thicker SiN capping layer enhances drive current, the reliability concerns on CVS and HCI become huger when thicker SiN capping layer deposited. More interface states are generated in high CVS of nMOSFET with thicker SiN layer. This expresses that a higher amount of hydrogen incorporated during SiN deposition as well as the high strain energy stored in the channel. For nMOSFET devices with SiN layer, compared CVS and HCI, we find that HCI cause less threshold voltage shift and interface state density shift than CVS. This shows that CVS phenomenon is more serious than HCI on HfO2/SiON gate stack.