完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.author | 王志賢 | en_US |
| dc.contributor.author | Chi-Shen Wang | en_US |
| dc.contributor.author | 黃宇中 | en_US |
| dc.contributor.author | Yu-Chung Huang | en_US |
| dc.date.accessioned | 2014-12-12T02:52:06Z | - |
| dc.date.available | 2014-12-12T02:52:06Z | - |
| dc.date.issued | 2006 | en_US |
| dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#GT009311645 | en_US |
| dc.identifier.uri | http://hdl.handle.net/11536/78114 | - |
| dc.description.abstract | 電容式感測器廣用於各種量測裝置。本論文中主要設計一個通用式電容感測器的介面電路,其內部元件包括電容對電壓轉換器、電壓對頻率轉換器及數位線性度補償器。 電容-頻率轉換器以交換電容式積分器為主要的架構。內部的時脈產生器產生時脈控制開關係由不同的電容值輸出不同的方波頻率完成。此轉換電路具有實現容易且不需要類比轉數位電路的優點,因此設計成本可以大為降低。該轉換器電路使用偏移電壓抵補技術來補償以達到最小偏移誤差,且可抗拒寄生電容效應。在傳統交換電容轉換出來高頻的部份非線性的問題,在此以數位電路補償的方法來改善。 此電容-頻率轉換器以TSMC 0.35μm 2P4M CMOS製程製作晶片,展示的電容範圍為4p~24p,對應的頻率範圍0.5K~500KHz。電源供應為3.3V,晶片面積占940 × 1080μm2,整個晶片的功率為6mW。驗證採用電容式壓力感測器,模擬的結果驗證此介面電路小於10%的誤差。 | zh_TW |
| dc.description.abstract | Capacitive sensors are widely adapted to various measuring equipments. The objective goal of this thesis is to realize a general interface circuit of the capacitive sensor. The main componenet of this interface circuit are composed of capacitance-to-voltage converter, voltage-to-frequency converter and digital compensation circuit. The architecture of this capacitance-to-frequency convereter is based on the switch-capacitor integrator. Under the control of clock generator, this converter produces the square-wave whose frequency is dependent on the external capacitor. Because of the advantage of easier implementation and without ADC in front-end, its cost is low. The technique of offset-cancellation is implemented in this converter to eliminate the offset error. This converter is also insentitive to parasitic capacitance. Moreover, we improve the non-linearity issue in traditional architecture by adding the digital compensation circuit. This capacitance-to-frequency converter is fabricated in TSMC 0.35um 2P4M CMOS technology process. The capacitor range is 4p~24p which correspond to frequency from 0.5KHz to 500KHz. The power supply is 3.3V, chip area is 940 × 1080μm2 and power comsumption is 6mW. The simulation results show that the error of this converter is less than 10%. | en_US |
| dc.language.iso | zh_TW | en_US |
| dc.subject | 感測器 | zh_TW |
| dc.subject | 電容-頻率轉換器 | zh_TW |
| dc.subject | 數位補償器 | zh_TW |
| dc.subject | sensor | en_US |
| dc.subject | Capacitance-to-Frequency Converter | en_US |
| dc.subject | Compensation | en_US |
| dc.title | 補償示電容-頻率轉換器 | zh_TW |
| dc.title | A Compensation Capacitance-to-Frequence Converter | en_US |
| dc.type | Thesis | en_US |
| dc.contributor.department | 電子研究所 | zh_TW |
| 顯示於類別: | 畢業論文 | |

