1.25億位元/每秒四分之ㄧ時脈與資料回復電路設計與實現

Abstract

隨著資料在高速傳輸的需求日益增加，其資料的正確性和時脈的穩定性在類比與數位電路系統中更顯重要，包含通訊系統、有線與無線網路、頻率調變訊號的解調、電腦與周邊設備的連結及各網域間的連線等，我們已經利用光纖媒介來達到高頻和低損耗的傳輸[1]，但在接收端更需小心的確保資料流並沒有因雜訊的累加而放大了誤差。資料與時脈回復器在此即扮演了關鍵角色，將時脈從接收到的資料中取出並重新取樣被污染的資料。 本論文的主題在完成一個雙迴路的1.25Gb/s資料與時脈回復器，並且完全使用互補式金氧半製程來實現以達到低功率、高度整合的優點，為達到未來系統晶片強調的超低功率，我們更把時脈的頻率降低且在不影響速度的前提下達到成效。另一方面，省卻除頻器的架構改採解多路傳輸資料的方式。論文分為四章，第一章為簡介，第二章介紹光纖傳輸與資料和時脈回復器的背景，第三章為本論文設計的重點與模擬結果，第四章是比較其他篇論文, 最後總結整個設計以及針對未來設計提出建議。

With the increasing demand of high speed transport of data, it is more important that the accuracy of data and the stability of clock in analog and digital systems. Fibers provide much greater bandwidths and lower losses in many areas, inclusive of communication systems, wireline and wireless network, demodulation of frequency-modulated signals, many high speed links between computers and other peripheral, and the connection of such LAN/WAN, etc. But we must be more careful not to amplify the error by the jitter accumulation. Data and clock recovery plays a critical part here to extract the real clock from data and retime the dirty bits. The goal of this thesis is to use standard CMOS process to realize a 1.25Gb/s dual-loop data and clock recovery. To attain the aim of low power what we put emphasis on SOC, deep sub-micron CMOS technology is now being considered because of that advantages such as low power, highly integrated capacity. On the other hand, it does not require a frequency divider and we utilize demultiplexer to retime data. The paper could be divided into four chapters. Chapter 1 is the introduction. Chapter 2 presents the background of fiber transport and data and clock recovery. Chapter 3 is the purpose of mainly architecture and the simulation. Chapter 4 is the comparison with other papers. Finally, I summarize all design and give it some suggestion for future work.