完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yu, Jui-Yuan | en_US |
dc.contributor.author | Chen, Juinn-Ting | en_US |
dc.contributor.author | Yang, Mei-Hui | en_US |
dc.contributor.author | Chung, Ching-Che | en_US |
dc.contributor.author | Lee, Chen-Yi | en_US |
dc.date.accessioned | 2014-12-08T15:10:14Z | - |
dc.date.available | 2014-12-08T15:10:14Z | - |
dc.date.issued | 2007 | en_US |
dc.identifier.isbn | 978-1-4244-1592-2 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/7813 | - |
dc.description.abstract | An all-digital clock generator is designed to enable the clock phase and frequency tuning dynamically during the wireless communications system is in operation. This phase-frequency tunable clock generator (PFTCG) provides 8 clock phases for selection and enables the ADC circuits sampling signals with lower frequency and better sampling phase, resulting in lower power consumption. The PFTCG provides the frequency tuning range +/- 150ppm centered at 5MHz, resulting in high performance due to smaller sampling clock offset. This PFTCG is simulated under the wireless body area network system, and shows a 6.3dB SNR improvement at BER=1 e(-3), and the. hardware is simulated with power 77.56 mu M in the standard process 90nm CMOS technology. | en_US |
dc.language.iso | en_US | en_US |
dc.title | An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems | en_US |
dc.type | Article | en_US |
dc.identifier.journal | 20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | en_US |
dc.citation.spage | 305 | en_US |
dc.citation.epage | 308 | en_US |
dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
dc.identifier.wosnumber | WOS:000257572200068 | - |
顯示於類別: | 會議論文 |