應用於數位電視廣播規格之同步化系統設計

Abstract

在本論文中，我們提出了一個應用於數位電視廣播規格的同步化系統設計。此同步化系統設計由一組載波相位校準、取樣頻率漂移同步以及快速同步設計組成。我們團隊於2006年ISSCC期刊中發表的DVB-T/H基頻接收機設計為本篇論文的參考設計。我們提出的載波相位校準可以克服在Rayleigh衰減通道中，取樣頻率漂移20ppm、都卜勒頻率70Hz、載波頻率漂移10.3，、訊雜比34分貝，其中，傳輸模式為2K模式，Viterbi編碼率2/3。第二部份，與傳統設計相比，取樣頻率漂移估計的正確度相比可達到2~5倍；取樣頻率漂移追蹤也可達到3倍的收斂速度。快速同步的設計也比傳統設計的同步速度快上2~4.5倍，而在timing-slicing的架構下，也使得我們的電路功率消耗節省約莫百分之10，接收機記憶體減少1~3Mbits。在不同的傳輸模式以及通到效應下，整體的系統效能只比完美同步系統損失0~0.3分貝。並且在硬體上我們整合了同步系統電路中重複的部分，與ISSCC2006的設計相比，同步化設計電路的部份可以解省百分之46的硬體。

In this thesis, a synchronization system is proposed for Digital Video Broadcasting-Terrestrial/Handheld (DVB-T/H) standard. This synchronization system comprises 3 parts: carrier phase alignment, sampling clock synchronization, and fast synchronization schemes. In this paper, we take the DVB-T/H baseband receiver [1] proposed in ISSCC2006 as the reference design. First, the proposed carrier phase alignment can overcome sampling clock offset (SCO) 20ppm, Doppler frequency 70Hz, carrier frequency offset (CFO) 10.3 at Rayleigh fading channel with SNR 34dB in 2K mode and Viterbi coderate 2/3. Second, comparing with conventional design, the SCO estimation accuracy can reach 2~5 times; SCO tracking can obtain the convergent time 3 times fast. Then, the fast synchronization can increase the speed of synchronization 2~4.5 times. Under time-sling architecture, the saving of power consumption can improve about 10% and receiver buffer is decreased 1~3Mbits. The overall performances are only lose 0~0.3dB in different transmission modes. Finally, on the vision of hardware, we integrate the similar part of synchronization algorithms and compare with [1] in ISSCC2006. We can save the hardware 46%.