具有使用者可調性主從式指令快取記憶體控制器之多核嵌入式處理器

Abstract

無論是在一般應用的嵌入式處理器(General Embedded Processor) 或是著重於運算的數位訊號處理器(Digital Signal Processor, DSP)，cache miss幾乎都是影響效能的一個很大的因素。由於cache miss的penalty常常都是數千週期甚至上萬週期，所以如果可以設計一個可以減少cache miss次數及總miss penalty的快取記憶體控制器，便可以有效的提升處理器的執行效能。本論文設計了一個可實現於晶片中的指令快取記憶體控制硬體演算法，此演算法使用在一般的應用程式均能有效的減少指令快取記憶體(I-Cache)的總miss penalty，而在具有大量迴圈運算及函式呼叫的多媒體應用程式中尤有顯著成效，為驗證該演算法的可靠性及正確性，本論文也設計出一個VLIW架構的多核心嵌入式處理器，以做為該指令快取記憶體控制器的作用平台，並整合成為一顆嵌入式處理器晶片。此晶片採用UMC 0.18μm 製程，以Cell-based方式設計，晶片面積約3.1x3.1 mm2，預估最大操作頻率在135MHz。

Cache miss is a very significant factor to affect its efficiency for the General Embedded Processor in general applications or the Digital Signal Processor(DSP) emphasizing on computing operations. The cache miss results in the penalty of wasting of thousands of cycles or more. For this reason, if we design a cache controller that can reduce the number of cache miss and save miss penalty, we will enhance the efficiency of the processor. In the paper, an I-Cache controller hardware algorithm that can be applied in Chip is introduced. When this algorithm is applied for general application program, it can efficiently reduce the total miss penalty of the I-Cache. Even more, we can see the significant effect when it is applied for the multi-media application that has many loop operations and function calls. In order to prove the dependability and the correctness of the algorithm, the thesis designs a multi-core embedded processor that has VLIW architecture. That can be used for the operation platform of the I-Cache controller, and be intergraded into a embedded processor chip. This Chip is fabricated in UMC 0.18μm process and designed in the way of Cell-based. The chip area is 3.1x3.1 mm2 , and the max operation frequency is operated at 135MHz.