802.11 媒體控制器之頻道速率WEP和DCF的ASIC實現

Abstract

目前有內建無線網路功能的設備愈來愈普遍，而且傳輸速度也比以前都來的更快。為了實現更高吞吐量的設計，以硬體為主的設計將更常被採用。 在這篇論文當中，我們提出符合IEEE 802.11 標準的硬體式媒體控制器及一硬體式WEP 加解密引擎。這兩者可以非常容易的整合進入內建無線網路功能的系統晶片(SoC)當中。 並且透過一先進先出的記憶體及 PLCP表頭的前奏時間來解決 RC4 演算法中執行 金鑰排程(Key Schedule Algorithm,KSA)時所消耗掉的時間.如此將可以在WEP 加解密功能打開下，802.11 MAC仍然可以維持54Mbps頻道速率的吞吐量。有關模擬環境方面 ，我們設計一個虛擬 802.11媒體控制器用來產生及檢查 802.11 的封包以驗證我們的設計。在對基頻處理器的介面訊號方面，我們選擇Intersil HFA3861B 及 HFA3683做為我們的實體層。 最後我們將完成支援 DCF的媒體控制器及一具有54Mbps頻道速率吞吐量的WEP 安全引擎 。所有的設計使用Verilog語言來完成 。這個設計可已完全被合成為電路 。而且在使用Xilinx FPGA (v2000efg1156-8)元件下，其操作頻率可以達到 44 MHz。 消耗的邏輯閘數是51,029 閘。

Embedded wireless communication devices nowadays are getting more and more popular and running at higher speeds than ever before. In order to achieve the desired throughput, the hardware approach is being adopted more often. In this thesis, we propose a hardware-based MAC IP that is compatible with IEEE 802.11 standard, and a hardware-based WEP IP. They both can be easily integrated into an SoC chip for embedded wireless communication devices. It uses FIFO RAM and PLCP preamble time to recover the overhead of processing KSA at RC4. Hence it can retain the throughput at 54Mbps Channel-speed with the WEP function turned on. In our simulation environment, a pseudo model of 802.11 MAC is designed to generate and check 802.11g frames to verify our implementation. For the baseband interface signals, we use the Intersil HFA3861B and HFA3683 as the physical layer. Finally, we accomplish an 802.11 MAC that support DCF machine and 54Mbps Channel-speed WEP security machine. All designs are accomplished by the Verilog RTL language. It is fully synthesizable and its operation frequency can scale up to 44MHz at the Xilinx FPGA (v2000efg1156-8) device. The total equivalent gate count is 51,029.