Word Line Delay 方法的研究 應用在 DRAM 可靠性 Poly Residue 的改善

Abstract

目前動態隨機存取記憶體（DRAM）的產品。除了容量越來越大以外，速度也越來越快，這是由於製程技術的進步，近幾年來由0.15um，0.11um，90nm一直到目前的70nm。當然這是量產的階段，實驗的階段都已經到達45nm。尤其製程的線寬及距離越來越小時，漏電會是一個相當嚴肅的問題。本論文要探討的就是電晶體的閘極，因為蝕刻濃度的配方沒有調整在最佳化時，導致閘極的多晶矽殘留，所引發的漏電。而論文的貢獻在於瞭解字元線的延遲，和多晶矽漏電的關係中，所探討的可靠性問題的研究。在有效的篩選出多晶矽的殘留時，同時也降低可靠性的問題，和傳統的測試比較，有效提升了可靠性及穩定的生產品質。

Currently DRAM (Dynamic Random Access Memory) product, in addition to the memory size is bigger and bigger, the speed is also quicker and quicker, this is due to the progress of manufacturing process technique, in the last few years by 0.15 um, 0.11 um, 90 nm until current of 70 nm. Certainly this is the stage of production, the stages of experiment all have already arrived 45 nm. Particularly wire breadth and distance of manufacturing process are smaller and smaller and the electric leakage will be a rather serious problem. This thesis wanting what to inquire into is the poly gate of transistor, because the formula of the etching concentration didn't adjust while optimizing and cause the poly residue of poly gate, the electric leakage caused. And the contribution of thesis that understands word line delay, in the relationship with poly-silicon electric leakage, the research of reliability problem inquired into. While effectively screen the poly residue, also reduce the problem of reliability, and traditional test compare, effectively promoted reliability and the production quality of stabilization.