容錯控制器架構之系統實現研究

Abstract

本論文以硬體描述語言為基礎，設計一組高可靠度的容錯控制器架構。整體架構上有別於一般常見的由三套處理器模組搭配俗稱投票器的多數表決控制器及匯流排架構結合之三組態容錯架構。而是將多數表決控制器的功能內嵌至各控制單元的交握過程，藉由三組控制單元彼此交握協調的過程中，在即時需求的時刻內產生正確的輸出值。

此架構有效的整合了多管線備份架構及三組態容錯架構兩者的優點，排除了當三組態備份架構中多數表決控制器出現異常狀態時導致全系統無輸出訊號之可能性。同時藉由硬體描述語言的平台設計，也降低了採用一般硬體方式實現多管線所需的龐大體積及高昂金錢之代價。

This thesis is to describe the design of a high reliability Fault-Tolerant controller utilizing the Hardware Description Language(HDL). Differing from TMR-based hybrid hardware which composed of three controller module、a Majority Voter and a data bus, the structure embeds the Majority Voter into the hand-shaking process of each control units. It is also designed to generate adequate output during hand-shaking process of three (3) controllers in response to real time requirement.

This architecture combines the advantage of Multi-Bus and TMR structure which despite possible failure of voter that may cause no output of system. By use of HDL, this architecture can save large amount of space and cost that traditional Hardware system may not be affordable.