覆晶共晶錫鉛銲錫接點 (5-um Cu 金屬墊層)之電遷移研究

Abstract

高接腳密度､縮減封裝體積等優勢，讓覆晶銲錫在電子產品走向輕、薄、短、小的趨勢中，成為進階元件的主流封裝型式。伴隨積體電路高電流､小尺寸的設計變化，覆晶銲錫接點內的電遷移現象成為元件可靠度的影響關鍵。在覆晶銲錫電遷移測試中，發現孔洞通常生成於導線與銲錫凸塊界面處。研究發現其係在電子流由導線進入銲錫時，因電子流流通面積劇變，造成電流集中效應的影響。 目前一般的覆晶銲錫凸塊高度約為50~100 -um，在本文研究中，將針對輕、薄、短、小的趨勢下，利用凱文結構作為覆晶銲錫凸塊電性的量測，觀察以5-um Cu UBM接合之銲錫凸塊高度20-um的覆晶共晶錫鉛銲錫，其各階段的電遷移破壞模式。研究發現，試片的電遷移破壞模式階段為銅金屬墊層消耗溶解､介金屬層成長､孔洞生成､成長､擴大至試片的完全破壞。

Flip-chip technology has become a mainstream trend in advanced electronic packaging because of its capability of higher I/O density and smaller package size. With higher current and smaller size trends, electromigration in flip-chip solder has become an critical of reliability concern. Currently, the bump height of solder bumps is about 50~100-um. In this study, we will follow the trend- toward light, thin, short, small and measure the resistance change of solder bumps in the electromigration effect by using the Kevin structure and observe its various stages of electromigration failure modes with the eutectic SnPb solder with 20-um bump height and 5-um thick Cu UBM (under-bump-metallization). In this study, we measure the resistance change of solder bumps in the electromigration effect by using the Kevin structure and observe their failure modes at various stages of electromigration with the eutectic SnPb solder, which is 20-um bump height and 5-um thick Cu UBM. We found that the electromigration failure mode in the solder specimens is the dissolution of copper UBM, the growing of IMC layer, the generation of void and the void extending into the rest of the contact open.