淺溝槽絕緣層製程於快閃記憶體產品填洞能力之改善

Abstract

快閃記憶體是目前非揮發性記憶體中發展的主流, 就快閃記憶體技術藍圖來說, 隨著集積度的增加及對低耗電的要求而需採用更先進之製程,因此對一些元件關鍵單位製程要求度便會提升。 本論文之研究主要是針對 0.12 微米快閃記憶體浅溝槽絕緣製程(Shallow Trench Isolation)之填洞能力及平坦度來做探討。目前動態隨機存取記憶體所用之製程參數，發現若以同步沉積蝕刻之方式來沉積淺溝槽絕緣層於快閃記憶體，無論調變合何種參數，對空洞及缺角化之改善有限，無法徹底解決，主要因為兩種產品之淺溝槽之深寬比差異太大，由於此缺陷會造成電性及良率之影響，故須找出各參數對空洞及缺角化之影響，方有幫助解決問題。因此由文獻得知以沉積蝕刻沉積是較有效之改善方式，因此便設計沉積╱蝕刻╱沉積，調變不同之參數及沉積蝕刻之厚度來同時解決空洞及缺角化之問題，最後以製程條件為最佳之參數設定，並有效將空洞及缺角化之問題同時解決，並可通過可靠度測試及可量產之條件。

Student: Ming-Kung Tsai Advisor：Dr. Chia-Fu Chen

Abstract

NAND FLASH memory is very popular nonvolatile memory all over the world so far. For higher density and lower power consumption requirement for FLASH memory, optimized key unit process is a key for device performance. This study evaluates the integration of gap fill capability and STI film uniformity for sub 0.12 μm and beyond. Current we suffer void and corner clipping issue in STI structure on 0.12μm DRAM Product whatever we modify any process parameter. The main reason is due to aspect ratio variation too big on sub 0.12 μm and beyond product. As we know, the gap fill of the trench has to be void free in STI process. Otherwise, it would impact CMP, Photo and Etch integration even WAT (wafer acceptance test) and yield. Unfortunately, corner clipping has to be enhanced after we try to fine tune process recipe to reduce void for STI process, which would cause WAT shift and yield loss. Based on past paper statement, using Dep/Etching/Dep would improve void and corner clipping issue at same time. Therefore, we design a experiment with Dep/Etching/Dep way to optimize process parameter to overcome void and corner clipping issue in STI process simultaneously. Beside, these products also pass wafer acceptance test and fully production criteria.