MPEG低複雜度先進音訊解碼器之硬體共用設計與實作

Abstract

本論文之研製之一種以硬體共用的方式來提高硬體使用率及降低硬體面積，對於功能運算硬體的重複使用，來設計低複雜度先進音訊解碼(Advance Audio Coding – Low Complexity)之硬體加速的解碼器架構。近年來對於音訊壓縮格式的研究與發展，以AAC最為廣泛的被使用，而這裡所採用的音訊標準規格為MPEG-2 AAC-LC。首先我們分析低複雜度先進音訊解碼的流程以及執行的相關功能，並進一步討論其相對使用之硬體架構。一般ASIC設計時，對每一功能方塊都會有其相對之硬體架構，依照各方塊來實現以及驗證。而在運算過程中，並不會所有的硬體都在執行，因此會有閒置的硬體存在，為了減少硬體的閒置，由MPEG-2 AAC-LC為基礎來設計可重用之硬體，來達提升硬體的使用率。以共用硬體架構來更可以進一步簡化提供給各功能所需要乘法器及加法器之運算，達到減少硬體面積的目標，我們所採用的架構製程是以台灣積體電路(TSMC)半導體0.18微米的製程，執行速度最快可運作在147MHz的時脈上，而重用硬體的設計將可降低47.89%的硬體面積與63.23%的功率消耗。

A procedure is applying a reusable hardware for part of Advance Audio Coding-Low Complexity decoder can be improved on hardware utilization and reduced the hardware area. In recent years, Advance Audio Coding in audio compression format is widely used for research and development. In here we adapted the audio standard is MPEG-2 AAC-Low Complexity. First, we analyzed the related functions in AAC-LC process and further discussion of the hardware architecture. In general, the ASIC design has its relative of the hardware architecture in each function. In the computing process, there are not all hardware process at the same time, there will be idle hardware exists. In order to reduce the idle hardware from the MPEG-2 AAC-LC, we can base on the reusable hardware to upgrade hardware usage. Reusable hardware architecture can be further simplified to provide the necessary functionality, multiplier and adder of computing. We adopted the framework process is Taiwan's integrated circuit (TSMC) semiconductor 0.18 micron process, the implementation of the fastest operational in 147 MHz clock rate, and the reuse of hardware design will be reduced 47.89 percent of the hardware area and 63.23% of power consumption.