标题: 利用矽锗氧与矽锗氮薄膜形成锗奈米点在非挥发性记忆体应用之研究
Study on Formation of Ge Nanocrystal using SiGeO and SiGeN layer for Nonvolatile Memory Applications
作者: 谢彦廷
Yen-Ting Hsieh
张俊彦
Chun-Yen Chang
电子研究所
关键字: 记忆体;非挥发性;奈米点;锗;Memory;Nonvolatile;Nanocrystal;Germanium
公开日期: 2006
摘要: 近年来,可携带式电子产品被广泛的使用,诸如数位像机、笔记型电脑、手机等等的产品,在市场上占有重要的地位。而这些产品都需要运用到非挥发性记忆体(NVM)作为储存资料中心,而非挥发性记忆体目前在元件尺寸持续的微缩下,其需求为高密度记忆单元、低功率损耗、快速读写操作以及良好的可靠度(Reliability)。然而传统浮动闸极(floating gate)记忆体在操作过程中,穿遂氧化层产生漏电路径会造成所有储存电荷流失回到矽基版,随着尺寸微缩这种情况会更糟,所以在资料保存时间(Retention)和耐操度(Endurance)的考量下,微缩穿遂氧化层的厚度是非常困难的。非挥发性奈米点记忆体及SONOS记忆体被提出希望可取代传统浮动闸极记忆体,由于彼此分离的储存点作为储存中心,所以上述两者可以有效改善小尺寸记忆体元件多次操作下的资料储存能力。
在本文中,我们提出一种矽锗氧(SiGeO)的堆叠结构作为作为锗奈米点(Ge nanocrystal)的自我析出层(self-assembled layer),并应用在奈米点非挥发性记忆体上。在室温下,在氩气及氧气(Ar/O2)的环境中溅镀(sputtering)矽锗(SixGe1-x)混合靶材,此方式可以成功的将氧掺入至矽锗中形成矽锗氧三元薄膜,另外,在我们的实验中,在热退火之前先叠加上一层氧化矽为一个关键的步骤。之后我们再利用矽与锗不同的氧化现象,经由快速热退火制成来形成均匀且高密度(~1012cm-2)的锗奈米点。并且我们延长热处理的时间可以有效的分离锗奈米点且减少奈米点周围氧化矽及氧化矽中的缺陷(defects),有效的降低电荷流失机率,改善资料保存时间。
同样地,我们用相同的方式,在溅镀的过程中将氧气置换成氮气,利用同样的方式制作锗奈米点且被包覆在氮化矽(SiNx)的结构,其记忆效应比先前的锗奈米点埋在氧化矽(SiOx)结构还显着,此乃因为锗奈米点埋在氮化矽为主的载子储存层中,会产生额外的储存中心,进而增加记忆体效能,另外,我们也延长热处理的时间,同样低可以改善锗奈米点间的隔离情况得到较大的记忆窗口,且改善资料保存时间。
另外,我们也尝试利用高介电常数介电质(ErSiGeO)当作我们的电荷储存层,可以有效的增加记忆体效应,且改善写入读取速度。以上这些应用在非挥发性记忆体的制成技术同时也适用于现阶段积体电路制程。
In recent years, the portable electronic products have widely applied, such as digit camera, laptop, cell phone and so on. These portable electronic products play an important role in the market, and these products are all based on the nonvolatile memory (NVM) for data storage center. Hence, the current requirements of NVM are the high density cells, low-power consumption, high-speed operation and good reliability for scaling down devices. However, all of the charges stored in the conventional floating gate NVM will leak back to substrate because the tunnel oxides have leakage paths during operation processes. It is even worse when being scaled down. Therefore, the thickness of tunnel oxide is difficult to scale down in terms of charge retention and endurance characteristics. The nonvolatile nanocrystal memory and SONOS memory are promising candidates to replace the conventional floating gate memory, because the discrete storage nodes of themselves are enveloped. Both of them are capable to improve data retention under operation and have been provided by the endurance test which is good for device further down scaling efficiently.
In this thesis, we proposed a SiGeO stacking structure serving as Ge nanocrystals self-assembled layer for application of nanocrystal NVM. We successfully incorporated oxygen into SiGe layer to form SiGeO ternary film by sputtering commixed SixGe1-x target in an Ar/O2 ambiance at room temperature. In additional we fond out that pre-annealing-capping oxide (PACO) is a critical step in our experimental process, and then we used the different oxidized mechanism between Si and Ge. The uniform and high density (~1012cm-2) of Ge nanocrystals was fabricated after a rapid thermal annealing (RTA) process. The Ge nanocrystals were isolated better and the defects (leakage path) in the SiOx which surrounds the nanocrystal were reduced by increasing the thermal treatment time. This process can reduce the probability of charges losing and improve the data retention time.
As the same, we used similar method that oxygen was replaced by nitrogen. The Ge nanocrystals embedded in SiNx structure was fabricated by using the same process. The memory window for the stacked structure with Ge NCs embedded in SiNx layer is larger than Ge NCs embedded in SiOx layer, due to the extra charge trapping centers generated for Ge NCs embedded SiNx layer. Furthermore, we also increased the time for thermal treatment resulting in better Ge NCs isolation and less defects in the SiNx. That improves the data retention time, too.
In addition, by using high dielectric constant layer (ErSiGeO) for charging tapping layer structure has better memory ability and the operation speed is improved, too. Finally, all of the above fabrication techniques for the application of nonvolatile nanocrystal memory can be compatible with current manufacture process of the integrated circuit manufacture.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009411553
http://hdl.handle.net/11536/80466
显示于类别:Thesis


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