互補式金氧半電流操作模式之射頻接收器前端電路設計與分析

Abstract

在這篇論文中，描述了低電壓、電流模式毫米波射頻前端電路的設計法及實現技巧。 本篇論文主要分三個部份，包含了 (1)利用電容回授的匹配網路技巧，來模組化、設計、以及分析低雜訊放大器；(2)低LO功率、九十度相位差、平衡架構、自行開關(self-switching)的電流模式混頻器的設計與分析；(3) 設計與分析一個擁有在兩百四十億赫茲的單晶片LO訊號產生器、以及直流偏移補償的1伏特電流模式接收機前端電路。

首先，一個針對於低雜訊放大器的新的輸入阻抗功率匹配技巧被提出。在所提出的技巧中，輸入共源極放大器的閘極-汲極電容及電容回授匹配網路被用來實現一個實數的輸入阻抗，以至於能和輸入源極阻抗匹配。使用這個技巧，能同時達到雜訊最小與功率增益最大，並且能在不耗損線性度下使用非常低的電源電壓。所提出的低雜訊放大器的雜訊分析由數學推導以及量測結果互相佐證。在此所提出之13GHz低雜訊放大器使用0.18贡m 1P6M金氧半製程技術實現。在量測結果上，增益(S21)為13.2分貝、雜訊指數(noise figure)為4.57分貝，以及最低雜訊指數(Fmin)為4.46分貝。此低雜訊放大器之隔絕(reverse isolation)可達-40分貝，在輸入及輸出阻抗匹配接低於-11分貝。在線性度部份，增益1分貝壓縮點為–11 dBm 與 三階互調失真點為–0.5 dBm。在供應電壓1伏特時低雜訊放大器之電流消耗為10mA。

其次，提出了一個毫米波射頻互補型金氧半、低LO功率、九十度相位差、平衡架構、自行開關(self-switching)的電流模式混頻器。此混頻器的組成，由一個輸入級的共閘極放大器、一個省面積的九十度分支線混合耦合器、以及金氧半自行開關(self-switching)的裝置。90度分支線混合耦合器被設計來處理在非常高頻上的射頻與LO訊號的結合。為了實現省面積的90度分支線混合耦合器，基於並聯電容的高阻抗耦合器波導，分支線及through-line由原來的四分之波長各自減少為六點四分之波長與十分之波長。所提出之混波器使用0.13–μm 1P8M 金氧半製程技術實現。在58GHz功率為0dBm之LO訊號下， 能將60–GHz 射頻訊號降至2–GHz中頻訊號。在這次設計中，此混波器之單端轉換增益(single-end conversion gain)為1分貝，其輸入增益1分貝壓縮點為2 dBm。LO與RF訊號隔絕可達到–37分貝，在供應電壓1.2伏特時其電流消耗為3mA。

最後，在此發表工業-科學-醫學接收器操作在24GHz。此接收機由一個低雜訊放大器、射頻混頻器、IF混頻器，直流偏移補償、電壓控制振盪器、以及一個除二電路。在論文第一部份所提及的低雜訊放大器，在貢獻最小的雜訊下用來放大在兩百四十億赫茲的射頻訊號，以增大接收訊號與雜訊間的差距。被增大的兩百四十億赫茲的射頻輸入訊號再經由論文第二部份所提及的射頻混頻器降頻至八十億赫茲的IF頻段。隨後的IF混頻器分成等相位與九十度相位差兩條路徑，把IF頻率直接降頻至零。此兩基頻訊號再利用直流偏移補償電路來消除在IF混頻器輸出端由LO自身混頻所產生的直流偏移。所提出之接收器使用0.13–μm 1P8M 金氧半製程技術實現，此接收器之增益為19.5分貝、雜訊指數為15分貝與輸入阻抗匹配(S11)皆低於-13分貝。其輸入增益1分貝壓縮點為–25dBm。在供應電壓1伏特時其電流消耗為35mA。

所提出的射頻電路及接收機前端電路相信能適用於設計高頻、高效能、低電壓、高整合度、全金氧半的毫米波無線通訊系統。在未來會在收發機上做更進一步的研究。

In this thesis, the design methodologies and implementation techniques of low-voltage current-mode high-frequency RF front-end circuits are presented. There are three parts in this thesis, including (1) the modeling, design, and analysis of low-noise amplifier utilizing the technique of capacitive feedback matching network; (2) the design and analysis of low LO-power quadrature balanced self-switching current-mode mixer; (3) the design and analysis of a 1-V current-mode front-end receiver with on chip LO signal generator and DC-offset compensation circuit at 24-GHz RF application. At first, a new input impedance power matching technique for LNA is proposed and analyzed, In the proposed technique, the gate-drain capacitor of the input common-source amplifier and the capacitive feedback matching network are used to implement a real input impedance in order to match with the input source impedance. Thus the technique is called technique of capacitive feedback matching network. By using this technique, the minimum noise figure and maximum power gain can be achieve simultaneously, furthermore, it can be used with very low supply voltage without degraded the linearity. The full noise analysis of LNA utilizing the proposed technique is supported by mathematical derivations and it is complemented and validated by measurements. Where, the proposed LNA which is implemented in a 0.18–μm 1P6M CMOS technology is operated at the frequency of 13 GHz. It has a gain S21 of 13.2 dB, a noise figure (NF) of 4.57 dB and an NFmin of 4.46 dB. The reverse isolation S12 of the LNA can achieve –40 dB and the input and output return losses are better than –11 dB. The input 1-dB compression point is –11 dBm and IIP3 is –0.5 dBm. This LNA drains 10 mA from the supply voltage of 1 V. Secondly, mm-wave RF CMOS low LO-power quadrature balanced self-switching current-mode mixer is proposed. The mixer consists of common-gate amplifier as input stage, an area efficient 90-degree branch-line hybrid coupler, and CMOS self-switching current-mode devices, the 90-dgree branch-line hybrid coupler is designed to deal with the issue on the combination of RF and LO signals at very high frequency, in order to implement area efficient 90-dgree branch-line hybrid coupler, the branch-line and the through-line lengths of the hybrid are reduced from lamda/4 to lamda/6.4 and lamda/10, respectively, based on the methodology of a high-impedance coplanar waveguide with shunt lumped capacitors. The proposed mixer, using 0.13–μm 1P8M CMOS technology, can down-convert 60–GHz RF signal to 2–GHz intermediate frequency (IF) signal, with a LO power of 0 dBm at 58 GHz. In the design, the mixer had a single-end conversion gain of 1dB and an input-referred 1dB compression point of 2 dBm. The LO-RF isolation of the mixer can achieve –37dB while using 3 mA from a supply voltage of 1.2V. Finally, Industrial-Science-Medical (ISM) receiver operates at 24 GHz is proposed. The receiver consists of transconductance low-noise amplifier (TLNA), RF current-mode mixer, IF current-mode mixers, DC-offset compensation, voltage control oscillator (VCO), and quadrature divided-by-two circuit (QD2). The TLNA proposed in the first part of the thesis is used to amplified the RF input spectrum at 24 GHz with minimal noise contribution to enlarge the power difference between the received signal and noise, then the amplified RF input spectrum at 24 GHz is down-converted to an intermmediate frequency (IF) of 8 GHz by using RF current-mode mixer proposed in the second part of the thesis, and a follow-up IF current-mode mixers are used in-phase I and quadrature Q paths to directly convert the spectrum at IF frequency to zero frequency. The baseband signals are then applied to the DC-offset compensation circuit to eliminate DC-offset currents appear at the output of the IF current-mode mixer due to the self-mixing of the LO. The fabricated circuit in 0.13–μm 1P8M CMOS technology demonstrates a conversion gain of 19.5 dB, and noise figure of 15 dB, while maintaining an input return loss better than –13-dB. The input-referred 1dB compression point of –25 dBm is measured. This receiver drains 35 mA from the supply voltage of 1 V.

It is believed that the proposed RF circuits and receiver front-end can be applied to the design of high-frequency high-performance low-voltage high-integration all-CMOS wireless communication systems. Future research on transceiver components will be conducted in the future.