以溶膠法製備之多重結構的鋯酸鍶記憶體元件之電阻轉換特性研究

Abstract

近來由於傳統快閃式記憶體(flash memory)在不斷微縮化下，面臨到許多急欲克服之難題，例如儲存在懸浮閘極(floating gate)中之電荷，因穿遂氧化層(tunneling oxide)過薄而隨著時間漸漸流失，喪失其非揮發記憶效應，另外，在長時間操作之下，易於穿遂氧化層內產生缺陷以及操作電壓過高…等，如此瓶頸，實為下世代非揮發性記憶體研究之首要課題。然而，眾多前瞻性非揮發性記憶體研究中，電阻式記憶體為利用電壓或電流脈衝在極短時間下改變電阻值，並藉由元件內部電阻值之不同作為其相對應之記憶狀態，進而達到資料寫入之動作。 本實驗首先在二氧化矽(200奈米)/矽基板上鍍製白金下電極(80奈米)，接著沉積厚度為100奈米之鎳酸鑭(LaNiO3) 為緩衝層，接著再利用溶膠凝膠法製備鋯酸鍶電阻薄膜(20~60奈米)，最後鍍上300奈米厚之鋁上電極，完成Al/SrZrO3/LaNiO3/Pt實驗結構。藉由改變元件結構以增加其導電率，導致鋯酸鍶薄膜於低偏壓下即有大量電流通過，使得鋯酸鍶薄膜不需任何摻雜便具有電阻轉態現象;但由於此元件在連續操作下，兩記憶狀態不穩定；因此問題，本實驗欲改變其原本結構，在鋯酸鍶層內嵌入一5奈米厚之鉻金屬層，即為六層薄膜結構(Al/SrZrO3/Cr/SrZrO3/LaNiO3/Pt)，隨後經由快速熱退火處理使鉻擴散至鋯酸鍶層內部，以改善元件兩記憶狀態不穩定之問題。

Recently, due to continuously scaling down for the conventional flash memory, there are many issues need to be overcome, such as the charge stored in the floating gate lost due to direct tunneling current or defects formed in the tunneling oxide during long-term operation. Therefore, the investigation of the next-generation nonvolatile memory is going to be the main topics. Among various next-generation nonvolatile memories, resistance random access memory store the data by change the resistance in the memory cell, which can be altered by voltage or current pulse in a short time leading to the write/erase operation. In this experiment, an 80-nm-thick Pt bottom electrode was deposited on SiO2/Si substrate, and follow by a 100-nm-thick LaNiO3 buffer layer. By sol-gel method, the 20-60nm SrZrO3 thin films were fabricated, and finally, the 300-nm-thick Al top electrode were deposited to fabricating the Al/SrZrO3/LaNiO3/Pt structure. By modifying the device structure, the resistive switching behaviors can be observed in the SrZrO3 films without any dopant. Moreover, to solve the variations during successive operation, the device structure is modified again into 6 layers structure: Al/SrZrO3/Cr/SrZrO3/LaNiO3/Pt, which shows excellent electrical properties.