奈米快閃記憶體之特性與研究

Abstract

傳統的非揮發性記憶體是利用複晶矽浮停閘(floating gate)做為載子儲存的單元,當浮停閘儲存由通道注入的電子之後,元件的起始電壓就會發生改變,利用起始電壓的差異作為記憶體0 和1 邏輯的定義。隨著系統晶片(SOC)的發展，持續降低互補式金氧半(CMOS)場效電晶體元件中的閘極判電層及非揮發性記憶體(non-volatile memories)中的複晶矽層間介電層(inter-poly dielectric)厚度以提高元件密度及降低操作電壓變得十分重要。但當氧化層厚度小於7奈米時，原本儲存於複晶矽浮停閘內的電荷，很容易因為氧化層中的缺陷，形成漏電流路徑，一旦穿隧氧化層(tunnel oxide)出現漏電路徑,儲存的電荷就會全部流失,記憶體就會失效。於是，以奈米點(nano dot)為儲存介質的新式NVM結構被提出以作為離散式儲存方式的記憶體，以順應尺寸微縮以及維持好的儲存能力等特性。在本篇論文中，我們利用金屬材料來製作出以奈米點或薄膜做為補陷電子媒介的記憶體 利用半導體或金屬奈米點作為電荷儲存的單元，在元件的反覆操作下,即使穿隧氧化層產生缺陷或漏電路徑,所損失掉的儲存電子,僅是單一奈米點的電子漏失,對整體元件特性的影響並不明顯。因此,穿隧氧化層的厚度得以縮減,使得操作速度提升,元件積集度增加,元件可操作的次數(endurance)以及保存時間(retention)也同時得到改善，當電子儲存在奈米點時,由於庫倫阻絕(Coulomb blockade)效應,儲存的電子會限制後續電子的注入。奈米點的庫倫阻絕效應使得記憶體元件的儲存及操作更加的穩健。

首先，本研究提出於穿隧氧化層上利用雙電子槍蒸鍍系統將金屬材料-鉑(Pt)沉積在試片上，之後覆蓋上SiO2做為控制氧化層，再經由高溫退火使之形成奈米點，以製造出奈米點結構記憶體。藉由這種方法我們可以得到具有低外加偏壓、大記憶窗口、快速寫入/抹除速度、高穩定性的非揮發性記憶體。同時，我們也預測可以用元件做一個單元儲存兩個位元的操作方式。因此，我們認為，利用Pt作為奈米點結構記憶體的材料是很有潛力且備受期待的。

In a conventional nonvolatile memory, charge is stored in a polysilicon floating gate (FG) surrounded by dielectrics. The scaling limitation stems from the requirement of very thin tunnel oxide layer. For FG, once the tunnel oxide develops a leakage path under repeated write/erase operation, all the stored charge will be lost. For the system-on-chip (SOC) application, a continuously scaling of the gate dielectrics for complementary metal oxide semiconductor (CMOS) and inter-poly dielectrics (IPDs) for electrically-erasable programmable read-only-memory (EEPROM) and stacked-gate flash memory is needed to obtain high density and low operation voltage. But when oxide thickness is less than 7nm, the charge stored in the floating gate forming leakage path easily due to defects in the oxide, thus induces data error. To overcome the limits of the conventional FG structure, other kinds of nonvolatile memories such as SONOS and nanocrystal memories which stored electrons in discrete traps are mostly mentioned, hence several characteristics such as scaling down and good storage maintenance can be reached. In this thesis, we successfully fabricated nanocrystral memory device by using metal materials. Nanocrystal charge storage offers several advantages, the main one being the potential to use thinner tunnel oxide without sacrificing nonvolatile. This is a quite attractive proposition since reducing the tunnel oxide thickness is a key to lowering operating voltages and/or increasing operating speeds. The improved scalability results not only from the distributed nature of the charge storage, which makes the storage more robust and fault-tolerant, but also from the beneficial effects of Coulomb blockade. A local leaky path will not cause a fatal loss of information for the nanocrystal nonvolatile memory device. Also, the nanocrystal memory device can maintain good retention characteristics and lower the power consumption.

First, a Platinum metal material layer was deposited on the oxide by Dual E-gun Evaporation System with Pt targets, then cap with SiO2. After that, the wafer was subjected to RTA treatment in N2 ambient at some temperature and time. When the film is RTA treated to provide enough energy and surface mobility, the thin Platinum material will self-assemble in to nano dot. By using the method, we obtain nonvolatile memory devices with excellent characteristics：low applied voltages, large memory window, high program/erase speed, fine endurance. And, we forecast that can use these devices in 2-bit operation . Consequently, we consider, it is potential material as nanocrystal memory devices by using Platinum.